Patents by Inventor Marie S. Cole
Marie S. Cole has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180194554Abstract: A fully integrated, low maintenance, manually operated beverage container compacting system featuring a free-standing, user powered, enclosed, beverage container compactor and storage receptacle. The compactor includes a self retracting puncture mechanism to release pressure due to air and liquids in sealed containers prior to their compacting. The storage system includes double trap doors with gaskets to create a sealed storage receptacle that reduces odors. A first top trap door includes a rubber gasket to prevent liquids from being expelled out of the compactor; and a bottom trap door is configured for capturing escaped liquids. The bottom trap door is actuated into an open state at an end of a crushing stroke to drop the container into the storage receptacle after captured liquids have drained into a liquid capture container for improved cleanliness. A self reset mechanism renders the system to an initial state for a next user after compacting.Type: ApplicationFiled: January 12, 2017Publication date: July 12, 2018Inventors: Marie S. Cole, Michael R. Kane, Suraush Q. Khambati, Colin E. Masterson, James A. O'Connor, Jacob T. Porter
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Patent number: 7566649Abstract: Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the device with an insulating underfill.Type: GrantFiled: September 20, 2007Date of Patent: July 28, 2009Assignee: International Business Machines CorporationInventors: William E. Bernier, Tien-Jen Cheng, Marie S. Cole, David E. Eichstadt, Mukta G. Farooq, John A. Fitzsimmons, Lewis S. Goldmann, John U. Knickerbocker, Tasha E. Lopez, David J. Welsh
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Patent number: 7442878Abstract: Disclosed is a laminated (or non-laminated) conductive interconnection for joining an integrated circuit device to a device carrier, where the conductive interconnection comprises alternating metal layers and polymer layers. In addition, the polymer can include dendrites, metal projections from the carrier or device, and/or micelle brushes on the outer portion of the polymer. The polymer layers include metal particles and the alternating metal layers and polymer layers form either a cube-shaped structure or a cylinder-shaped structure.Type: GrantFiled: October 5, 2006Date of Patent: October 28, 2008Assignee: International Business Machines CorporationInventors: William E. Bernier, Marie S. Cole, Mukta G. Farooq, John U. Knickerbocker, Tasha E. Lopez, Roger A. Quon, David J. Welsh
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Patent number: 7332821Abstract: Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the device with an insulating underfill.Type: GrantFiled: August 20, 2004Date of Patent: February 19, 2008Assignee: International Business Machines CorporationInventors: William E. Bernier, Tien-Jen Cheng, Marie S. Cole, David E. Eichstadt, Mukta G. Farooq, John A. Fitzsimmons, Lewis S. Goldmann, John U. Knickerbocker, Tasha E. Lopez, David J. Welsh
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Patent number: 7325213Abstract: A structure for a system of chip packages includes a master substrate and at least one subset substrate of the master substrate. The subset substrate includes a portion of the master substrate that has an identical pin out pattern as the portion of the master substrate. The subset substrate has identical internal net lists as the portion of the master substrate. The subset substrate is adapted to accommodate a smaller chip than the master substrate. The master substrate is the largest substrate in the system. The invention also prepares a system of chip packages. The invention selects a master substrate and then selects a subset substrate of the master substrate.Type: GrantFiled: June 17, 2005Date of Patent: January 29, 2008Assignee: International Business Machines CorporationInventors: Harsaran S. Bhatia, Marie S. Cole, Michael S. Cranmer, Jason Lee Frankel, Eric Kline, Kenneth A. Papae, Paul R. Walling
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Patent number: 7170187Abstract: Disclosed is a laminated (or non-laminated) conductive interconnection for joining an integrated circuit device to a device carrier, where the conductive interconnection comprises alternating metal layers and polymer layers. In addition, the polymer can include dendrites, metal projections from the carrier or device, and/or micelle brushes on the outer portion of the polymer. The polymer layers include metal particles and the alternating metal layers and polymer layers form either a cube-shaped structure or a cylinder-shaped structure.Type: GrantFiled: August 31, 2004Date of Patent: January 30, 2007Assignee: International Business Machines CorporationInventors: William E. Bernier, Marie S. Cole, Mukta G. Farooq, John U. Knickerbocker, Tasha E. Lopez, Roger A. Quon, David J. Welsh
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Patent number: 5147084Abstract: Disclosed is a connector structure on a substrate which includes at least one first solder portion on the surface of the substrate; at least one second solder portion connected to each of the at least one first solder portions; and an epoxy layer disposed about the at least one first and second solder portions in such a manner as to cover the first solder portion and contact, but not cover, the second solder portion. Also disclosed is a connector structure on a substrate which includes at least one first solder portion on the surface of said substrate; at least one second solder ball portion connected to the at least one first solder portions; wherein the melting point of the second solder ball portion is relatively higher than that of the first solder portion. Finally, disclosed is a method of testing the solderability of the above structures.Type: GrantFiled: August 9, 1991Date of Patent: September 15, 1992Assignee: International Business Machines CorporationInventors: John R. Behun, Anson J. Call, Francis F. Cappo, Marie S. Cole, Karl G. Hoebener, Bruno T. Klingel, John C. Milliken
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Patent number: 5060844Abstract: Disclosed is a connector structure on a substrate which includes at least one first solder portion on the surface of the substrate; at least one second solder portion connected to each of the at least one first solder portions; and an epoxy layer disposed about the at least one first and second solder portions in such a manner as to cover the first solder portion and contact, but not cover, the second solder portion.Also disclosed is a connector structure on a substrate which includes at least one first solder portion on the surface of said substrate; at least one second solder ball portion connected to the at least one first solder portions; wherein the melting point of the second solder ball portion is relatively higher than that of the first solder portion.Finally, disclosed is a method of testing the solderability of the above structures.Type: GrantFiled: July 18, 1990Date of Patent: October 29, 1991Assignee: International Business Machines CorporationInventors: John R. Behun, Anson J. Call, Francis F. Cappo, Marie S. Cole, Karl G. Hoebener, Bruno T. Klingel, John C. Milliken