Patents by Inventor Mario Caresosa
Mario Caresosa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10313104Abstract: In some aspects, the disclosure is directed to methods and systems for controlling periodic jitter arising from a phase interpolator (PI). A receiver can receive incoming data. A fractional-N phase-locked loop (PLL) can receive a reference clock. Measurement circuitry can measure a parts per million (PPM) offset between the incoming data and the reference clock, of a PI. The fractional-N PLL can restrict jitter arising from the PI, to frequencies within a predefined bandwidth, by tuning a center frequency of the fractional-N PLL to reduce the PPM offset of the PI.Type: GrantFiled: September 18, 2017Date of Patent: June 4, 2019Assignee: Avago Technologies International Sales Pte. LimitedInventors: Amiad Dvir, Mike Rolfe Ferrara, Vitaly Zborovski, Mario Caresosa, Ryan Hirth, Assaf Naor
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Publication number: 20190089520Abstract: In some aspects, the disclosure is directed to methods and systems for controlling periodic jitter arising from a phase interpolator (PI). A receiver can receive incoming data. A fractional-N phase-locked loop (PLL) can receive a reference clock. Measurement circuitry can measure a parts per million (PPM) offset between the incoming data and the reference clock, of a PI. The fractional-N PLL can restrict jitter arising from the PI, to frequencies within a predefined bandwidth, by tuning a center frequency of the fractional-N PLL to reduce the PPM offset of the PI.Type: ApplicationFiled: September 18, 2017Publication date: March 21, 2019Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Amiad Dvir, Mike Rolfe Ferrara, Vitaly Zborovski, Mario Caresosa, Ryan Hirth, Assaf Naor
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Patent number: 7974337Abstract: Various example embodiments are disclosed. According to an example embodiment, an apparatus may include a continuous time filter, a decision feedback equalizer, a clock and data recovery circuit, and an adaptation circuit. The adaptation circuit may be configured to adapt equalization according to at least one dithering algorithm by adjusting a delay adjust signal based on a mean square error of equalized data signals.Type: GrantFiled: October 27, 2009Date of Patent: July 5, 2011Assignee: Broadcom CorporationInventors: Afshin Momtaz, Mario Caresosa, David Kyong-Sik Chung, Davide Tonietto, Guangming Yin, Bruce Currivan, Thomas Kolze, Ichiro Fujimori
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Publication number: 20100046601Abstract: Various example embodiments are disclosed. According to an example embodiment, an apparatus may include a continuous time filter, a decision feedback equalizer, a clock and data recovery circuit, and an adaptation circuit. The adaptation circuit may be configured to adapt equalization according to at least one dithering algorithm by adjusting a delay adjust signal based on a mean square error of equalized data signals.Type: ApplicationFiled: October 27, 2009Publication date: February 25, 2010Applicant: Broadcom CorporationInventors: Afshin Momtaz, Mario Caresosa, David Chung, Davide Tonietto, Guangming Yin, Bruce Currivan, Thomas Kolze, Ichiro Fujimori
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Patent number: 7623600Abstract: Equalization is provided in a high speed communication receiver that includes in various aspects an automatic gain control input stage, a decision feedback equalizer, a clock and data recovery circuit and equalization control circuits. The automatic gain control stage may include a continuous time filter with an adjustable bandwidth. A threshold adjust signal may be applied to the output of the automatic gain control stage. The equalization control circuits may be implemented in the digital domain and operate at a lower clock speed than the data path.Type: GrantFiled: June 30, 2004Date of Patent: November 24, 2009Assignee: Broadcom CorporationInventors: Afshin Momtaz, Mario Caresosa, David Chung, Davide Tonietto, Guangming Yin, Bruce Currivan, Thomas Kolze, Ichiro Fujimori
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Patent number: 7522847Abstract: A communication system having a transmitter transmits an information signal over a communication media and a receiver coupled to the communication media receives the transmitted information signal. The receiver includes a continuous time filter having an adjustable bandwidth for linearly equalizing the transmitted information signal as a function of the adjustable bandwidth. A decision feedback equalizer coupled to the continuous time filter then reduces inter-symbol interference in the filtered information signal.Type: GrantFiled: February 9, 2004Date of Patent: April 21, 2009Assignee: Broadcom CorporationInventors: Afshin Momtaz, Mario Caresosa
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Patent number: 7496133Abstract: An apparatus and method are disclosed to aid a transceiver chip, in a wide-band serial data communications system, in receiving data at multiple data rates. A multi-rate filter within the transceiver chip is implemented as at least one adjustable-rate filter stage and a limiting stage. The at least one adjustable-rate filter stage is used to generate a filtered serial data signal from a received serial data signal. The limiter stage generates a full-swing serial data signal from the filtered serial data signal. A bandwidth of the at least one adjustable-rate filter stage is adjustable in order to receive serial data signals at multiple data rates. The bandwidth of the multi-rate filter within the transceiver chip is selectable by the user of the wide-band communication system.Type: GrantFiled: November 19, 2002Date of Patent: February 24, 2009Assignee: Broadcom CorporationInventors: Ichiro Fujimori, Mario Caresosa, Namik Kocaman
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Patent number: 7391838Abstract: A phase lock loop comprising a plurality of voltage controlled oscillators is presented herein. The phase lock loop can provide a wide range of output frequencies with low jitter. Additionally, the phase lock loop can be incorporated into a clock multiplier unit and a clock and data recovery unit.Type: GrantFiled: May 22, 2003Date of Patent: June 24, 2008Assignee: Broadcom CorporationInventors: Mario Caresosa, Namik Kocaman
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Publication number: 20080130679Abstract: Present herein is a multirate transceiver wherein data can be received at a first data rate and transmitted at a second data rate. The transceiver device comprises a first interface for receiving data at one data rate a mapper that can map data from a first rate to the second rate, and a second interface for transmitting the data at the second data rate.Type: ApplicationFiled: November 1, 2007Publication date: June 5, 2008Inventors: Vikram Natarajan, Kang Xiao, Mario Caresosa, Jay Proano, David Chung, Afshin Momtaz, Randy Stolaruk, Xin Wang, Namik Kocaman
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Patent number: 7356076Abstract: A method and apparatus are disclosed to aid a transceiver chip, in a serial data communications system, in recovering from a system-side, out-bound data clocking problem. If a problem with a primary clock signal, used to clock data from a system-side of a transceiver chip through at least a part of an out-bound data path of the transceiver chip, is detected, then a more reliable secondary clock signal is substituted for the primary clock signal. Once it is determined that the primary clock signal has recovered, the primary clock signal is switched back to and certain discrete circuits of the out-bound data path of the transceiver chip are automatically reset in hardware without the need for system level intervention to avoid any problems due to clock glitches on the primary clock signal during the switching.Type: GrantFiled: December 5, 2002Date of Patent: April 8, 2008Assignee: Broadcom CorporationInventors: Kang Xiao, Mario Caresosa, Hongtao Jiang, Randall Stolaruk
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Patent number: 7324548Abstract: Present herein is a multirate transceiver wherein data can be received at a first data rate and transmitted at a second data rate. The transceiver device comprises a first interface for receiving data at one data rate a mapper that can map data from a first rate to the second rate, and a second interface for transmitting the data at the second data rate.Type: GrantFiled: January 31, 2003Date of Patent: January 29, 2008Assignee: Broadcom CorporationInventors: Vikram Natarajan, Kang Xiao, Mario Caresosa, Jay Proano, David Chung, Afshin Momtaz, Randy Stolaruk, Xin Wang, Namik Kocaman
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Patent number: 7262659Abstract: A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.Type: GrantFiled: November 13, 2006Date of Patent: August 28, 2007Assignee: Broadcom CorporationInventors: Mario Caresosa, Guangming Yin
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Publication number: 20070069817Abstract: A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.Type: ApplicationFiled: November 13, 2006Publication date: March 29, 2007Inventors: Mario Caresosa, Guangming Yin
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Patent number: 7135926Abstract: A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.Type: GrantFiled: September 29, 2005Date of Patent: November 14, 2006Assignee: Broadcom CorporationInventors: Mario Caresosa, Guangming Yin
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Patent number: 7053720Abstract: A phase lock loop with multiple divider paths is presented herein. The phase lock loop can be used to provide a wide range of frequencies. The phase lock loop can also be used as a portion of a clock multiplier unit or a clock data and recovery unit.Type: GrantFiled: February 2, 2005Date of Patent: May 30, 2006Assignee: Broadcom CorporationInventors: Mario Caresosa, Namik Kocaman, Afshin Momtaz
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Patent number: 7042271Abstract: A compensation apparatus maintains an effective resistance of one or more resistors in a circuit by associating an adjustable resistor circuit to each resistor. The compensation apparatus compares the resistance of a resistor in the circuit with the resistance of a reference resistor. When the resistance of the resistor in the circuit falls outside of a desired range, the compensation apparatus adjusts the resistance of the adjustable resistor to adjust the effective resistance of the resistor and adjustable resistor combination.Type: GrantFiled: May 6, 2004Date of Patent: May 9, 2006Assignee: Broadcom CorporationInventors: David Kyong-Sik Chung, Afshin Momtaz, Mario Caresosa
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Patent number: 7034606Abstract: An input processing circuit includes a first and second input transistors for receiving a differential pair of first and second input signals, respectively. At least one resistor is coupled between first terminals of the first and second input transistors. The input processing circuit includes a variable gain amplifier (VGA) circuit. At least one first transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. At least one second transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. A gate switch is coupled to the gate terminal of the at least one second transistor. The at least one first transistor and the at least one second transistor adjust a gain of the input processing circuit in response to a control voltage.Type: GrantFiled: May 7, 2004Date of Patent: April 25, 2006Assignee: Broadcom CorporationInventors: Mario Caresosa, Afshin Momtaz, Guangming Yin
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Publication number: 20060028270Abstract: A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.Type: ApplicationFiled: September 29, 2005Publication date: February 9, 2006Inventors: Mario Caresosa, Guangming Yin
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Patent number: 6980053Abstract: A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.Type: GrantFiled: May 24, 2004Date of Patent: December 27, 2005Assignee: Broadcom CorporationInventors: Mario Caresosa, Guangming Yin
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Patent number: RE45557Abstract: A phase lock loop with multiple divider paths is presented herein. The phase lock loop can be used to provide a wide range of frequencies. The phase lock loop can also be used as a portion of a clock multiplier unit or a clock data and recovery unit.Type: GrantFiled: July 3, 2013Date of Patent: June 9, 2015Assignee: Broadcom CorporationInventors: Mario Caresosa, Namik Kocaman, Afshin Momtaz