Patents by Inventor Mario Giuseppe Saggio

Mario Giuseppe Saggio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220262913
    Abstract: A vertical-conduction MOSFET device formed in a body of silicon carbide having a first and a second face and a peripheral zone. A drain region, of a first conductivity type, extends in the body between the two faces. A body region, of a second conductivity type, extends in the body from the first face, and a source region, having the first conductivity type, extends to the inside of the body region from the first face of the body. An insulated gate region extends on the first face of the body and comprises a gate conductive region. An annular connection region, of conductive material, is formed within a surface edge structure extending on the first face of the body, in the peripheral zone. The gate conductive region and the annular connection region are formed by a silicon layer and by a metal silicide layer overlying the silicon layer.
    Type: Application
    Filed: February 10, 2022
    Publication date: August 18, 2022
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Mario Giuseppe SAGGIO, Alfio GUARNERA, Cateno Marco CAMALLERI
  • Patent number: 11417778
    Abstract: A merged-PN-Schottky, MPS, diode includes an N substrate, an N-drift layer, a P-doped region in the drift layer, an ohmic contact on the P-doped region, a plurality of cells within the P-doped region and being portions of the drift layer where the P-doped region is absent, an anode metallization on the ohmic contact and on said cells, to form junction-barrier contacts and Schottky contacts respectively. The P-doped region has a grid-shaped layout separating from one another each cell and defining, together with the cells, an active area of the MPS diode. Each cell has a same geometry among quadrangular, quadrangular with rounded corners and circular; and the ohmic contact extends at the doped region with continuity along the grid-shaped layout.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: August 16, 2022
    Assignee: STMicroelectronics S.R.L.
    Inventors: Simone Rascuna′, Mario Giuseppe Saggio
  • Publication number: 20220246723
    Abstract: A vertical conduction MOSFET device includes a body of silicon carbide having a first conductivity type and a face. A metallization region extends on the face of the body. A body region of a second conductivity type extends in the body, from the face of the body, along a first direction parallel to the face and along a second direction transverse to the face. A source region of the first conductivity type extends towards the inside of the body region, from the face of the body. The source region has a first portion and a second portion. The first portion has a first doping level and extends in direct electrical contact with the metallization region. The second portion has a second doping level and extends in direct electrical contact with the first portion of the source region. The second doping level is lower than the first doping level.
    Type: Application
    Filed: January 19, 2022
    Publication date: August 4, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe SAGGIO, Alessia Maria FRAZZETTO, Edoardo ZANETTI, Alfio GUARNERA
  • Publication number: 20220246729
    Abstract: A vertical conduction MOSFET device includes a body of silicon carbide, which has a first type of conductivity and a face. A superficial body region of a second type of conductivity has a first doping level and extends into the body to a first depth , and has a first width. A source region of the first type of conductivity extends into the superficial body region to a second depth, and has a second width. The second depth is smaller than the first depth and the second width is smaller than the first width. A deep body region of the second type of conductivity has a second doping level and extends into the body, at a distance from the face of the body and in direct electrical contact with the superficial body region, and the second doping level is higher than the first doping level.
    Type: Application
    Filed: December 29, 2021
    Publication date: August 4, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe SAGGIO, Edoardo ZANETTI, Alessia Maria FRAZZETTO, Alfio GUARNERA, Cateno Marco CAMALLERI, Antonio Giuseppe GRIMALDI
  • Publication number: 20220246771
    Abstract: A vertical conduction electronic device is formed by a body of wide-bandgap semiconductor material having a first conductivity type and a surface, which defines a first direction and a second direction. The body has a drift region. The electronic device includes a plurality of superficial implanted regions having a second conductivity type, which extend in the drift region from the surface and delimit between them, in the drift region, at least one superficial portion facing the surface. At least one deep implanted region has the second conductivity type, and extends in the drift region, at a distance from the surface of the body. A metal region extends on the surface of the body, in Schottky contact with the superficial portion of the drift region.
    Type: Application
    Filed: February 3, 2022
    Publication date: August 4, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Simone RASCUNA', Gabriele BELLOCCHI, Edoardo ZANETTI, Mario Giuseppe SAGGIO
  • Publication number: 20220208977
    Abstract: An electronic device comprising: a semiconductor body of silicon carbide, SiC, having a first and a second face, opposite to one another along a first direction, which presents positive-charge carriers at said first face that form a positive interface charge; a first conduction terminal, which extends at the first face of the semiconductor body; a second conduction terminal, which extends on the second face of the semiconductor body; a channel region in the semiconductor body, configured to house, in use, a flow of electrons between the first conduction terminal and the second conduction terminal; and a trapping layer, of insulating material, which extends in electrical contact with the semiconductor body at said channel region and is designed so as to present electron-trapping states that generate a negative charge such as to balance, at least in part, said positive interface charge.
    Type: Application
    Filed: March 18, 2022
    Publication date: June 30, 2022
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Patrick FIORENZA, Fabrizio ROCCAFORTE, Mario Giuseppe SAGGIO
  • Publication number: 20220208961
    Abstract: A MOSFET transistor device includes a functional layer of silicon carbide, having a first conductivity type. Gate structures are formed on a top surface of the functional layer and each includes a dielectric region and an electrode region. Body wells having a second conductivity type are formed within the functional layer, and the body wells are separated from one another by surface-separation regions. Source regions having the first conductivity type are formed within the body wells, laterally and partially underneath respective gate structures. Modified-doping regions are arranged in the surface-separation regions centrally thereto, underneath respective gate structures, in particular underneath the corresponding dielectric regions, and have a modified concentration of dopant as compared to the concentration of the functional layer.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 30, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Patrick FIORENZA, Fabrizio ROCCAFORTE, Edoardo ZANETTI, Mario Giuseppe SAGGIO
  • Publication number: 20220157807
    Abstract: An integrated MOSFET device is formed in a body of silicon carbide and with a first type of conductivity. The body accommodates a first body region, with a second type of conductivity; a JFET region adjacent to the first body region; a first source region, with the first type of conductivity, extending into the interior of the first body region; an implanted structure, with the second type of conductivity, extending into the interior of the JFET region. An isolated gate structure lies partially over the first body region, the first source region and the JFET region. A first metallization layer extends over the first surface and forms, in direct contact with the implanted structure and with the JFET region, a JBS diode.
    Type: Application
    Filed: February 2, 2022
    Publication date: May 19, 2022
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Mario Giuseppe SAGGIO, Simone RASCUNÁ
  • Publication number: 20220157989
    Abstract: A MOSFET device comprising: a structural region, made of a semiconductor material having a first type of conductivity, which extends between a first side and a second side opposite to the first side along an axis; a body region, having a second type of conductivity opposite to the first type, which extends in the structural region starting from the first side; a source region, having the first type of conductivity, which extends in the body region starting from the first side; a gate region, which extends in the structural region starting from the first side, traversing entirely the body region; and a shielding region, having the second type of conductivity, which extends in the structural region between the gate region and the second side. The shielding region is an implanted region self-aligned, in top view, to the gate region.
    Type: Application
    Filed: February 4, 2022
    Publication date: May 19, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe SAGGIO, Edoardo ZANETTI
  • Patent number: 11329131
    Abstract: A MOSFET device includes a semiconductor body having a first and a second face. A source terminal of the MOSFET device includes a doped region which extends at the first face of the semiconductor body and a metal layer electrically coupled to the doped region. A drain terminal extends at the second face of the semiconductor body. The doped region includes a first sub-region having a first doping level and a first depth, and a second sub-region having a second doping level and a second depth. At least one among the second doping level and the second maximum depth has a value which is higher than a respective value of the first doping level and the first maximum depth. The metal layer is in electrical contact with the source terminal exclusively through the second sub-region.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: May 10, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Edoardo Zanetti, Alfio Guarnera
  • Patent number: 11316025
    Abstract: An electronic device comprising: a semiconductor body of silicon carbide, SiC, having a first and a second face, opposite to one another along a first direction, which presents positive-charge carriers at said first face that form a positive interface charge; a first conduction terminal, which extends at the first face of the semiconductor body; a second conduction terminal, which extends on the second face of the semiconductor body; a channel region in the semiconductor body, configured to house, in use, a flow of electrons between the first conduction terminal and the second conduction terminal; and a trapping layer, of insulating material, which extends in electrical contact with the semiconductor body at said channel region and is designed so as to present electron-trapping states that generate a negative charge such as to balance, at least in part, said positive interface charge.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: April 26, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Patrick Fiorenza, Fabrizio Roccaforte, Mario Giuseppe Saggio
  • Publication number: 20220076955
    Abstract: A manufacturing method of an anchorage element of a passivation layer, comprising: forming, in a semiconductor body made of SiC and at a distance from a top surface of the semiconductor body, a first implanted region having, along a first axis, a first maximum dimension; forming, in the semiconductor body, a second implanted region, which is superimposed to the first implanted region and has, along the first axis, a second maximum dimension smaller than the first maximum dimension; carrying out a process of thermal oxidation of the first implanted region and second implanted region to form an oxidized region; removing said oxidized region to form a cavity; and forming, on the top surface, the passivation layer protruding into the cavity to form said anchorage element fixing the passivation layer to the semiconductor body.
    Type: Application
    Filed: August 26, 2021
    Publication date: March 10, 2022
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Simone RASCUNA', Mario Giuseppe SAGGIO
  • Patent number: 11270993
    Abstract: An integrated MOSFET device is formed in a body of silicon carbide and with a first type of conductivity. The body accommodates a first body region, with a second type of conductivity; a JFET region adjacent to the first body region; a first source region, with the first type of conductivity, extending into the interior of the first body region; an implanted structure, with the second type of conductivity, extending into the interior of the JFET region. An isolated gate structure lies partially over the first body region, the first source region and the JFET region. A first metallization layer extends over the first surface and forms, in direct contact with the implanted structure and with the JFET region, a JBS diode.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: March 8, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Mario Giuseppe Saggio, Simone Rascuná
  • Patent number: 11251296
    Abstract: A MOSFET device comprising: a structural region, made of a semiconductor material having a first type of conductivity, which extends between a first side and a second side opposite to the first side along an axis; a body region, having a second type of conductivity opposite to the first type, which extends in the structural region starting from the first side; a source region, having the first type of conductivity, which extends in the body region starting from the first side; a gate region, which extends in the structural region starting from the first side, traversing entirely the body region; and a shielding region, having the second type of conductivity, which extends in the structural region between the gate region and the second side. The shielding region is an implanted region self-aligned, in top view, to the gate region.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: February 15, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Edoardo Zanetti
  • Publication number: 20220028978
    Abstract: Merged-PiN-Schottky, MPS, device comprising: a substrate of SiC with a first conductivity; a drift layer of SiC with the first conductivity, on the substrate; an implanted region with a second conductivity, extending at a top surface of the drift layer to form a junction-barrier, JB, diode with the substrate; and a first electrical terminal in ohmic contact with the implanted region and in direct contact with the top surface to form a Schottky diode with the drift layer. The JB diode and the Schottky diode are alternated to each other along an axis: the JB diode has a minimum width parallel to the axis with a first value, and the Schottky diode has a maximum width parallel to the axis with a second value smaller than, or equal to, the first value. A breakdown voltage of the MPS device is greater than, or equal to, 115% of a maximum working voltage of the MPS device in an inhibition state.
    Type: Application
    Filed: July 13, 2021
    Publication date: January 27, 2022
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Simone RASCUNÁ, Mario Giuseppe SAGGIO
  • Publication number: 20210399089
    Abstract: An electronic device includes a semiconductor body of silicon carbide, and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly at the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.
    Type: Application
    Filed: June 14, 2021
    Publication date: December 23, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe SAGGIO, Angelo MAGRI', Edoardo ZANETTI, Alfio GUARNERA
  • Patent number: 11177394
    Abstract: A switching device including: a body of semiconductor material, which has a first conductivity type and is delimited by a front surface; a contact layer of a first conductive material, which extends in contact with the front surface; and a plurality of buried regions, which have a second conductivity type and are arranged within the semiconductor body, at a distance from the contact layer.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: November 16, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Simone Rascuna'
  • Publication number: 20210328022
    Abstract: A method for manufacturing a SiC-based electronic device, comprising the steps of: implanting, on a front side of a solid body made of SiC having a conductivity of an N type, dopant species of a P type thus forming an implanted region, which extends in the solid body starting from the front side and has a top surface coplanar with the front side; and generating a laser beam directed towards the implanted region in order to generate heating of the implanted region to temperatures comprised between 1500° C. and 2600° C. so as to form a carbon-rich electrical-contact region at the implanted region. The carbon-rich electrical-contact region forms an ohmic contact.
    Type: Application
    Filed: April 8, 2021
    Publication date: October 21, 2021
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Simone RASCUNÁ, Mario Giuseppe SAGGIO, Giovanni FRANCO
  • Publication number: 20210280424
    Abstract: A method for manufacturing an electronic device based on SiC includes forming a structural layer of SiC on a front side of a substrate. The substrate has a back side that is opposite to the front side along a direction. Active regions of the electronic device are formed in the structure layer, and the active regions are configured to generate or conduct electric current during the use of the electronic device. A first electric terminal is formed on the structure layer, and an intermediate layer is formed at the back side of the substrate. The intermediate layer is heated by a LASER beam in order to generate local heating such as to favor the formation of an ohmic contact of Titanium compounds. A second electric terminal of the electronic device is formed on the intermediate layer.
    Type: Application
    Filed: March 3, 2021
    Publication date: September 9, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventors: Simone RASCUNA', Paolo BADALA', Anna BASSI, Mario Giuseppe SAGGIO, Giovanni FRANCO
  • Publication number: 20210249268
    Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.
    Type: Application
    Filed: April 29, 2021
    Publication date: August 12, 2021
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Edoardo ZANETTI, Simone RASCUNA', Mario Giuseppe SAGGIO, Alfio GUARNERA, Leonardo FRAGAPANE, Cristina TRINGALI