Patents by Inventor Mario Mazzola

Mario Mazzola has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190203980
    Abstract: The invention relates to a refrigeration plant with multiple evaporation levels, operating according to a vapour compression cycle and comprising a circuit 2 having a high-pressure branch HP, wherein is arranged at least one heat exchanger 10, and two or more low-pressure branches LP1,LP2,LP3, each of which operates at a different evaporation level to serve users having different refrigeration requirements. In each of the low-pressure branches the plant comprises an expansion device 11?,11?,11??, at least one evaporator 12?,12?,12?? and a compressor group 13?,13?,13??. Said at least one evaporator of each low-pressure branch LP1, LP2, LP3 is connected directly to said high-pressure branch HP. At least a first low-pressure branch LP1 comprises a liquid separator 20? that is fluidically connected: —to the evaporator outlet 12? to collect the liquid exiting the evaporator itself in the case in which the latter is operating in overfeeding conditions; and —to the intake of the compressor group 13?.
    Type: Application
    Filed: May 16, 2017
    Publication date: July 4, 2019
    Inventors: Paolo CAVALLERI, Mario DE BONA, Daniele MAZZOLA
  • Patent number: 9405698
    Abstract: This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the channel and configuring the set of field effect transistors to couple the channel with the sub-channel. In the example embodiment, data may be allowed to flow between the memory controller and the location in the memory over the channel and the sub-channel.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: August 2, 2016
    Assignee: Cisco Technology, Inc.
    Inventors: Mario Mazzola, Satyanarayana Nishtala, Luca Cafiero, Philip Manela
  • Patent number: 9100313
    Abstract: A multi-stage network switch comprises a plurality of ingress port subsystems each comprising one or more ingress ports configured to receive packets. The switch also comprises a plurality of unscheduled crossbar switching elements connected to the ingress port subsystems that are configured to receive one or more packets from at least one of the ingress port subsystems. The switch further comprises a plurality of egress port subsystems each comprising a memory and a plurality of egress ports. The memory comprises at least one shared egress buffer configured to receive any packets forwarded by the crossbar switching elements from the ingress port subsystems directed to the egress port subsystem, and the egress ports are configured to transmit the packets received in the shared egress buffer.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: August 4, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: Mario Mazzola, Luca Cafiero, Francis Matus, Georges Akis, Peter Newman
  • Publication number: 20140331095
    Abstract: This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the channel and configuring the set of field effect transistors to couple the channel with the sub-channel. In the example embodiment, data may be allowed to flow between the memory controller and the location in the memory over the channel and the sub-channel.
    Type: Application
    Filed: July 21, 2014
    Publication date: November 6, 2014
    Inventors: Mario Mazzola, Satyanarayana Nishtala, Luca Cafiero, Philip Manela
  • Patent number: 8825965
    Abstract: This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the channel and configuring the set of field effect transistors to couple the channel with the sub-channel. In the example embodiment, data may be allowed to flow between the memory controller and the location in the memory over the channel and the sub-channel.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: September 2, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Mario Mazzola, Satyanarayana Nishtala, Luca Cafiero, Philip Manela
  • Patent number: 8621132
    Abstract: This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving first initialization data from a physical dual inline memory module (DIMM) and converting the first initialization data to second initialization data of a logical DIMM mapped to the physical DIMM. The example embodiment may further include programming a memory controller based on the second initialization data.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: December 31, 2013
    Assignee: Cisco Technology, Inc.
    Inventors: Mario Mazzola, Satyanarayana Nishtala, Luca Cafiero, Dmitry Barsky
  • Patent number: 8407394
    Abstract: This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes detecting a memory command directed to a logical rand and a number of physical ranks mapped to the logical rank. The example embodiment may also include issuing the memory command to the number of physical ranks based on determining that the memory command is to be issued to the number of physical ranks.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: March 26, 2013
    Assignee: Cisco Technology, Inc.
    Inventors: Mario Mazzola, Satyanarayana Nishtala, Luca Cafiero, Philip Manela
  • Publication number: 20090177861
    Abstract: This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving first initialization data from a physical dual inline memory module (DIMM) and converting the first initialization data to second initialization data of a logical DIMM mapped to the physical DIMM. The example embodiment may further include programming a memory controller based on the second initialization data.
    Type: Application
    Filed: January 8, 2008
    Publication date: July 9, 2009
    Inventors: Mario Mazzola, Satyanarayana Nishtala, Luca Cafiero, Dmitry Barsky
  • Publication number: 20090177853
    Abstract: This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes detecting a memory command directed to a logical rand and a number of physical ranks mapped to the logical rank. The example embodiment may also include issuing the memory command to the number of physical ranks based on determining that the memory command is to be issued to the number of physical ranks.
    Type: Application
    Filed: January 8, 2008
    Publication date: July 9, 2009
    Inventors: Mario Mazzola, Satyanarayana Nishtala, Luca Cafiero, Philip Manela
  • Publication number: 20090177849
    Abstract: This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the channel and configuring the set of field effect transistors to couple the channel with the sub-channel. In the example embodiment, data may be allowed to flow between the memory controller and the location in the memory over the channel and the sub-channel.
    Type: Application
    Filed: January 8, 2008
    Publication date: July 9, 2009
    Inventors: Mario Mazzola, Satyanarayana Nishtala, Luca Cafiero, Philip Manela
  • Publication number: 20040139167
    Abstract: An apparatus and method for a scalable network attached storage system. The apparatus includes a scalable network attached storage system, the network attached storage system including one or more termination nodes, one or more file server nodes for maintaining file systems, one or more disk controller nodes for accessing storage disks respectively, and a switching fabric coupling the one or more termination node, file server nodes, and disk controller nodes. The one or more termination nodes, file server nodes and disk controller nodes can be scaled as needed to meet user demands.
    Type: Application
    Filed: December 6, 2002
    Publication date: July 15, 2004
    Applicant: Andiamo Systems Inc., A Delaware Corporation
    Inventors: Thomas James Edsall, Mario Mazzola, Prem Jain, Silvano Gai, Luca Cafiero, Maurilio De Nicolo
  • Patent number: 5796732
    Abstract: A switching bus architecture enables efficient transfer of data within a network switch having a plurality of ports interconnected by a high-performance switching bus. The architecture is preferably implemented as novel port interface and forwarding engine circuitry that cooperate to efficiently transmit data to, and receive data from, the switching bus in accordance with a 2-tier arbitration policy that ensures adequate port access to the bus. As a result of such a cooperating arrangement, the architecture improves the transfer efficiency of the switch by providing all ports sufficient bus access to convey accurate data throughout the switch.
    Type: Grant
    Filed: March 28, 1996
    Date of Patent: August 18, 1998
    Assignee: Cisco Technology, Inc.
    Inventors: Mario Mazzola, Tom Edsall, Massimo Prati, Luca Cafiero
  • Patent number: 5740171
    Abstract: An address translation mechanism quickly and efficiently renders forwarding decisions for data flames transported among ports of a high-performance switch on the basis of, inter alia, virtual local area network (VLAN) associations among the ports. The translation mechanism comprises a plurality of forwarding tables, each of which contains entries having unique index values that translate to selection signals for ports destined to received the data frames. Each port is associated with a unique index value and a VLAN identifier to facilitate multicast data transfers within the switch at accelerated speeds and addressing capabilities.
    Type: Grant
    Filed: March 28, 1996
    Date of Patent: April 14, 1998
    Assignee: Cisco Systems, Inc.
    Inventors: Mario Mazzola, Tom Edsall, Luca Cafiero
  • Patent number: 5411365
    Abstract: In an opposed flow high pressure section, intermediate pressure section steam turbine (10), an annular section divider (142) is located axially between the high pressure section (HP) and the intermediate pressure section (IP), and substantially eliminates conventional inner shell sections. Thus, the turbine has only a single outer shell to which the blades of the turbine stages outside the divider 142 are operatively sealed. The section divider (142) incorporates partial arc steam admission chambers (150); supports a nozzle plate assembly (146); and includes integral steam packing (156) to seal the rotor interface.
    Type: Grant
    Filed: December 3, 1993
    Date of Patent: May 2, 1995
    Assignee: General Electric Company
    Inventors: Mario A. Mazzola, Thomas J. Farineau, George Schlottner, Earl H. Brinkman
  • Patent number: 5392513
    Abstract: A process for replacing a multi-piece steampath in a nozzle box (12) where, initially, the steampath (22) is secured between upper (24) and lower (26) ring components by means of axially accessible, arcuate welds (36, 38) includes the steps of:a) axially machining the arcuate welds (36, 38) so as to permit removal of the steampath (22) in a direction axially away from the nozzle box;b) further machining a forward portion of the lower ring component to provide a substantially vertical weld surface; andc) securing a one-piece steampath (222) in place by an axially accessible upper weld (236) and a radially accessible lower weld (238).
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: February 28, 1995
    Assignee: General Electric Co.
    Inventors: Mario Mazzola, Michael T. Hamlin, Richard I. Cromer, John Costantini
  • Patent number: 5280500
    Abstract: A multilevel encoding scheme for transmitted data that encodes data in a multilevel code wherein the amplitude of any transition is always exactly one level during any time interval. A single-level transition between any two adjacent levels during a time interval represents a logical "1"; no transition during a time interval represents a logical "0". In a specific embodiment, modulation is limited to three defined amplitude levels equally space in amplitude and encoding is according to a three-level code. A four-bit to five-bit encoding scheme may be used to distribute bits for minimizing d.c. offset. The input data is preferably further scrambled to minimize aberrations in the emissions spectrum of signal carried over unshielded media.
    Type: Grant
    Filed: October 10, 1991
    Date of Patent: January 18, 1994
    Assignee: Crescendo Communications, Inc.
    Inventors: Mario Mazzola, Luca Cafiero, Maurilio DeNicolo
  • Patent number: 4584690
    Abstract: A high-speed digital transceiver is provided for use in a PBX environment comprising twisted-pair wire cables interconnecting like transceivers, each transceiver being operative to exchange voice, data and control information in a packetized format over a common twisted-pair cable. Specifically, each transceiver communicates packetized pulse code modulated information in pure Alternate Mark Inverted (AMI) coding, that is, without the introduction of bipolar violation pulses to provide timing. Frame synchronization is acquired on the first pulse by the use of a digital circuit deriving synchronization from a local high-speed clock. The use of a high-speed clock-driven digital circuit for synchronization acquisition eliminates the need for a phase-locked loop synchronization scheme and its concomitant finite acquisition delay.
    Type: Grant
    Filed: May 7, 1984
    Date of Patent: April 22, 1986
    Assignee: D.A.V.I.D. Systems, Inc.
    Inventors: Luca Cafiero, Mario Mazzola, Massimo Prati
  • Patent number: 4292995
    Abstract: The locking valve apparatus includes a valve housing containing a rotatable cylinder lock with a keyway extending into the cylinder from one end and with a stationary cylindrical member of the valve housing encircling this rotatable cylinder. An alignment element on the outside of this stationary cylindrical member is adapted to position, align and guide a removable handle for the valve. This removable handle includes a sleeve defining a socket which is adapted to nest over the stationary cylindrical member of the valve housing when the handle is engaged for operating the valve. A key is located inside of this sleeve socket, being adjustably secured therein, and the socket is provided with a slot, which the user of the handle must align with the alignment element, otherwise the handle cannot be positioned on the valve housing.
    Type: Grant
    Filed: February 13, 1980
    Date of Patent: October 6, 1981
    Assignee: Richardson-Vicks Inc.
    Inventor: Mario Mazzola
  • Patent number: 4151565
    Abstract: A circuit for the decoding during reading of data prerecorded on a magnetic medium comprising a circuit for recognition of the recording code of the data recorded on the support by the recognition of the frequency of an input signal generated during the reading of the support and a frequency generating circuit controlled by the recognition circuit for generating a signal of predetermined frequency for the conversion of the recording code recognized into a binary code. A read-only memory comprising two zones is responsive to the recognition means for generating correcting words applied to a counter for controlling the position of a decoding window generated by a phase locked loop oscillator.
    Type: Grant
    Filed: May 6, 1977
    Date of Patent: April 24, 1979
    Assignee: Ing. C. Olivetti & C., S.p.A.
    Inventor: Mario Mazzola