Abstract: A multi-core processing system that uses computational sprinting to generate high levels of computational output for short periods of time at power consumption levels that are not sustainable over longer periods of time due to thermal and/or other constraints. This is done using a number of processing cores that, when operated simultaneously, utilize available thermal capacity within the system to consume power and produce heat that is in excess of a thermal design power (TDP) of the system, but is tolerable because of the short period of operation. The system and/or method described herein may include thermal capacitors in the form of phase change materials (PCMs), may implement normal, sprint and/or cooling modes of operation, and may employ parallel sprinting, frequency sprinting, sprint pacing and/or sprint-and-rest techniques, to cite several possibilities.

Abstract: Disclosed herein are digital systems and methods for use with a ramped clock signal. The digital system includes an input element having a data input to receive a data signal, a control input to receive a control signal, and a dynamic node to be driven by the ramped clock signal. The digital system further includes a static memory element having an input at the dynamic node and is configured to reside in an operational state in accordance with the data signal and the ramped clock signal. The input element further includes a switch coupled to the control input to condition updating of the operational state based on the control signal without decoupling the ramped clock signal from the dynamic node. In this way, distribution and delivery of the ramped clock signal to the digital system is continued to facilitate recovery of clock signal energy from the digital system.

Abstract: A boost circuit is disclosed that includes a plurality of transistors connected between complementary phases of a clock signal. The boost circuit further includes a first electrical node connected between at least two of the plurality of transistors wherein the plurality of transistors are configured to generate a second voltage from a first voltage at the electrical node in response to the clock signal.