Abstract: A bidirectional electroosmotic pump may be provided. The bidirectional electroosmotic pump may be made of materials that are biocompatible and non-ferrous. The bidirectional electroosmotic pump may be part of an implantable medical device for the purpose of medicine delivery. The bidirectional electroosmotic pump may contain a working fluid and may facilitate the delivery of a separate payload fluid. In an exemplary embodiment, the bidirectional pump may contain bellows which may allow the pump to deliver the payload fluid through a series of valves and/or catheters. In another embodiment the bidirectional electroosmotic pump may contain a pump sensing mechanism to monitor the state of the pump.

Abstract: A bidirectional electroosmotic pump may be provided. The bidirectional electroosmotic pump may be made of materials that are biocompatible and non-ferrous. The bidirectional electroosmotic pump may be part of an implantable medical device for the purpose of medicine delivery. The bidirectional electroosmotic pump may contain a working fluid and may facilitate the delivery of a separate payload fluid. In an exemplary embodiment, the bidirectional pump may contain bellows which may allow the pump to deliver the payload fluid through a series of valves and/or catheters. In another embodiment the bidirectional electroosmotic pump may contain a pump sensing mechanism to monitor the state of the pump.

Abstract: The specification discloses a method of doing business over the public Internet, particularly, a method which enables access to legacy management tools used by a telecommunications enterprise in the management of the enterprise business to the enterprise customer, to enable the customer to more effectively manage the business conducted by the customer through the enterprise, this access being provided over the public Internet. This method of doing business is accomplished with one or more secure web servers which manage one or more secure client sessions over the Internet, each web server supporting secure communications with the client workstation; a web page backplane application capable of launching one or more management tool applications used by the enterprise.

Abstract: A method and system to prefetch data from system memory to a central processing unit (CPU). The system includes a dynamic random access memory (DRAM) connected to a high speed bus, a CPU and a bus interface unit that allows the CPU to communicate with the high speed bus. The bus interface unit contains logic circuitry, so that when the CPU generates a read memory access request for information associated with a first address, the interface unit generates a request packet for the information and prefetch information associated with a prefetch address. The bus interface unit creates the request packet by increasing the number of addresses originally requested by the CPU. The interface then sends the request packet to the system memory device, which retrieves and returns the requested data. The interface may include a pair of buffers which store both the information requested by the CPU and speculative or prefetch information.

Abstract: Methods for of providing computer systems bundled with access to restricted-access databases. In one embodiment, a method includes providing a computer system with an authorized access identifier that allows access to a restricted-access database via a computer communication network; and providing the computer system to a user. The user is not required to pay use fees, or seek out a suitable information supplier, thereby improving user satisfaction and productivity. In an alternate embodiment, a method includes providing an access software program for accessing the restricted-access database. In another embodiment, a method includes generating the restricted-access database. Alternately, the generating of the restricted-access database may include storing educational information on a storage device, or transmitting an approximately real-time audio-visual signal. In another embodiment, a method includes updating the restricted-access database.

Abstract: A method and system for prefetching data from system memory to a central processing unit (CPU). The system includes a DRAM(s) connected to a high speed bus, CPU and a bus interface unit that allows the CPU to communicate with the high speed bus. The bus interface unit contains logic circuitry, so that when the CPU generates a read memory access request for information associated with a first address, the interface unit generates a request packet for the information and prefetch information associated with a prefetch address. The bus interface unit creates the request packet by increasing the number of addresses originally requested by the CPU. The interface then sends the request packet to the system memory device, which retrieves and returns the requested data. The interface may include a pair of buffers which store both the information requested by the CPU and the speculative information.

Abstract: Methods for of providing computer systems bundled with access to restricted-access databases. In one embodiment, a method includes providing a computer system with an authorized access identifier that allows access to a restricted-access database via a computer communication network; and providing the computer system to a user. The user is not required to pay use fees, or seek out a suitable information supplier, thereby improving user satisfaction and productivity. In an alternate embodiment, a method includes providing an access software program for accessing the restricted-access database. In another embodiment, a method includes generating the restricted-access database. Alternately, the generating of the restricted-access database may include storing educational information on a storage device, or transmitting an approximately real-time audio-visual signal. In another embodiment, a method includes updating the restricted-access database.

Abstract: A computer architecture that includes a high speed, low pin bus that directly couples a microprocessor to the physical memory of the processor. Physical memory typically has a number of dynamic random access memory (DRAM) devices. The bus is a byte wide and has a data rate of approximately 500 Mbytes/sec. The high speed bus may be coupled with a conventional bus, so that conventional devices can communicate with the processor using existing bus protocols. The present invention includes a processor interface that allows the processor to communicate using the protocol of either bus. The interface also allows communication between devices on either bus. Also included is a system that incorporates cache memory on a high speed memory bus and a method for allowing I/O devices to be placed on both a conventional bus and the separate high speed bus.

Abstract: A computer system, a bus interface unit, and a method for prefetching data from system memory to a central processing unit (CPU). The system includes a dynamic random access memory (DRAM) connected to a high speed bus, a CPU and a bus interface unit that allows the CPU to communicate with the high speed bus. The bus interface unit contains logic circuitry, so that when the CPU generates a read memory access request for information associated with a first address, the interface unit generates a request a packet for the information and prefetch information associated with a prefetch address. The bus interface unit creates the request packet by increasing the number of addresses originally requested by the CPU. The interface then sends the request packet to the system memory device, which retrieves and returns the requested data. The interface may include a pair of buffers which store both the information requested by the CPU and speculative or prefetch information.

Abstract: A computer architecture that includes a high speed, low pin bus that directly couples a microprocessor to the physical memory of the processor. Physical memory typically has a number of dynamic random access memory (DRAM) devices. The bus is a byte wide and has a data rate of approximately 500 Mbytes/sec. The high speed bus may be coupled with a conventional bus, so that conventional devices can communicate with the processor using existing bus protocols. The present invention includes a processor interface that allows the processor to communicate using the protocol of either bus. The interface also allows communication between devices on either bus. Also included is a system that incorporates cache memory on a high speed memory bus and a method for allowing I/O devices to be placed on both a conventional bus and the separate high speed bus.

Abstract: Methods for of providing computer systems bundled with access to restricted-access databases. In one embodiment, a method includes providing a computer system with an authorized access identifier that allows access to a restricted-access database via a computer communication network; and providing the computer system to a user. The user is not required to pay use fees, or seek out a suitable information supplier, thereby improving user satisfaction and productivity. In an alternate embodiment, a method includes providing an access software program for accessing the restricted-access database. In another embodiment, a method includes generating the restricted-access database. Alternately, the generating of the restricted-access database may include storing educational information on a storage device, or transmitting an approximately real-time audio-visual signal. In another embodiment, a method includes updating the restricted-access database.

Abstract: A computer architecture that includes a high speed, low pin bus that directly couples a microprocessor to the physical memory of the processor. Physical memory typically has a number of dynamic random access memory (DRAM) devices. The bus is a byte wide and has a data rate of approximately 500 Mbytes/sec. The high speed bus may be coupled with a conventional bus, so that conventional devices can communicate with the processor using existing bus protocols. The present invention includes a processor interface that allows the processor to communicate using the protocol of either bus. The interface also allows communication between devices on either bus. Also included is a system that incorporates cache memory on a high speed memory bus and a method for allowing I/O devices to be placed on both a conventional bus and the separate high speed bus.

Abstract: The present invention provides a method and apparatus for automatically scrubbing ECC errors in memory upon the detection of a correctable error in data read from memory. This is performed by providing in a memory controller memory control logic for controlling accesses to memory, an ECC error checking and correcting unit for checking data read from memory for errors and correcting any correctable errors found in the read data, a first data buffer for storing the corrected read data output from the ECC error checking and correcting unit and a writeback path having an input end coupled to an output of the first data buffer and an output end coupled to memory. Upon the detection of a correctable error in data read from a particular memory location, the ECC error checking and correcting unit signals to the memory control logic the existence of a correctable error in the read data.

Abstract: A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Requests originating on the second bus which target a destination on the first bus are placed into the inbound request queue. A transaction arbitration unit (TAU) within the bridge maintains transaction ordering and avoids deadlocks. The TAU determines whether requests can be placed in the inbound request queue. The TAU also determines whether requests originating on the first bus can be responded to immediately or whether the agent originating the request must wait for a reply. In addition, the TAU includes logic for determining whether a request in the outbound request queue can be executed on the second bus.

Abstract: A computer architecture that includes a high speed, low pin bus that directly couples a microprocessor to the physical memory of the processor. Physical memory typically has a number of dynamic random access memory (DRAM) devices. The bus is a byte wide and has a data rate of approximately 500 Mbytes/sec. The high speed bus may be coupled with a conventional bus, so that conventional devices can communicate with the processor using existing bus protocols. The present invention includes a processor interface that allows the processor to communicate using the protocol of either bus. The interface also allows communication between devices on either bus. Also included is a system that incorporates cache memory on a high speed memory bus and a method for allowing I/O devices to be placed on both a conventional bus and the separate high speed bus.

Abstract: A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Requests originating on the second bus which target a destination on the first bus are placed into the inbound request queue. A transaction arbitration unit (TAU) within the bridge maintains transaction ordering and avoids deadlocks. The TAU determines whether requests can be placed in the inbound request queue. The TAU also determines whether requests originating on the first bus can be responded to immediately or whether the agent originating the request must wait for a reply. In addition, the TAU includes logic for determining whether a request in the outbound request queue can be executed on the second bus.

Abstract: A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Requests originating on the second bus which target a destination on the first bus are placed into the inbound request queue. A transaction arbitration unit (TAU) within the bridge maintains transaction ordering and avoids deadlocks. The TAU determines whether requests can be placed in the inbound request queue. The TAU also determines whether requests originating on the first bus can be responded to immediately or whether the agent originating the request must wait for a reply. In addition, the TAU includes logic for determining whether a request in the outbound request queue can be executed on the second bus.

Abstract: A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Decoding circuitry within the bridge issues a deferred response if the request can be deferred. This deferred response is returned to the originating agent on the first bus, thereby informing the originating agent that the request will be serviced at a later time. Bus control circuitry coupled to the outbound request queue removes requests from the outbound request queue and executes them on the second bus. The bus control circuitry receives a response from the destination agent on the second bus in response to the execution of the outbound request. This response is returned to the originating agent either immediately or after passing through an inbound request queue.

Abstract: A method and apparatus for allowing two or more masters, such as central processing units (CPUs), to read a dynamic random access memory (DRAM) device which includes a cache connected to a main memory block. When a CPU provides a read request, the DRAM has a first logic circuit that compares addresses requested with addresses stored in the cache. If the addresses are the same, the DRAM sends an acknowledge (ACK) signal to that CPU and sends the data to the processor. If the addresses are not the same, the DRAM sends a no acknowledge (NACK) signal to the CPU and transfers the requested data from the main memory block to the cache. The DRAM has a second logic circuit that contains a latch which is set when the DRAM sends a NACK signal and reset when the DRAM sends a subsequent ACK signal. The second logic circuit is connected to the first logic circuit to disable the first logic circuit and prevent a cache fetch from main memory when the latch has been set.

Abstract: A method and apparatus for detecting and correcting errors in data transferred between a CPU and system memory. System memory typically has a number of dynamic random access memory (DRAM) devices that each have a block of memory cells. The DRAM also has an internal cache that contains a row of memory from a main memory block. Both the cache and block of memory cells contain vertical and horizontal parity bits. Each byte of data bits has an associated horizontal parity bit. Similarly a group of data bits having the same bit position will have an associated vertical parity bit. The parity bits are used to detect and correct errors in data transmissions between a CPU and system memory The cache includes arrays of exclusive OR (XOR) gates that can update the vertical parity bits when one or more bytes of data are written into the DRAM.