Patents by Inventor Mark Bohr

Mark Bohr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190115257
    Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
    Type: Application
    Filed: December 13, 2018
    Publication date: April 18, 2019
    Inventors: Abhijit Jayant PETHE, Tahir GHANI, Mark BOHR, Clair WEBB, Harry GOMEZ, Annalisa CAPPELLANI
  • Patent number: 10249588
    Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Sridhar Balakrishnan, Mark Bohr
  • Patent number: 10192783
    Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventors: Abhijit Jayant Pethe, Tahir Ghani, Mark Bohr, Clair Webb, Harry Gomez, Annalisa Cappellani
  • Publication number: 20180047808
    Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.
    Type: Application
    Filed: October 20, 2017
    Publication date: February 15, 2018
    Inventors: Milton Clair WEBB, Mark BOHR, Tahir GHANI, Szuya S. LIAO
  • Patent number: 9831306
    Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventors: Milton Clair Webb, Mark Bohr, Tahir Ghani, Szuya S. Liao
  • Publication number: 20170263721
    Abstract: Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.
    Type: Application
    Filed: May 30, 2017
    Publication date: September 14, 2017
    Applicant: INTEL CORPORATION
    Inventors: KELIN J. KUHN, KAIZAD MISTRY, MARK BOHR, CHRIS AUTH
  • Publication number: 20170084564
    Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
    Type: Application
    Filed: December 5, 2016
    Publication date: March 23, 2017
    Inventors: Valery M. DUBIN, Sridhar BALAKRISHNAN, Mark BOHR
  • Patent number: 9543261
    Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: January 10, 2017
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Sridhar Balakrishnan, Mark Bohr
  • Publication number: 20170004998
    Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
    Type: Application
    Filed: September 15, 2016
    Publication date: January 5, 2017
    Inventors: Abhijit Jayant Pethe, Tahir Ghani, Mark Bohr, Clair Webb, Harry Gomez, Annalisa Cappellani
  • Patent number: 9461143
    Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: October 4, 2016
    Assignee: Intel Corporation
    Inventors: Abhijit Jayant Pethe, Tahir Ghani, Mark Bohr, Clair Webb, Harry Gomez, Annalisa Cappellani
  • Publication number: 20160233298
    Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.
    Type: Application
    Filed: December 19, 2013
    Publication date: August 11, 2016
    Inventors: Milton C. WEBB, Mark BOHR, Tahir GHANI, Szuya S. LIAO
  • Publication number: 20150187900
    Abstract: An integrated circuit including a transistor, wherein the transistor includes a substrate including a surface, a gate oxide deposited on the substrate surface and a gate deposited on the gate oxide. The gate oxide includes one or more dielectric domains and a band gap matrix. The dielectric domains includes a first material and the band gap matrix includes a second material, wherein a dielectric constant of the first material is greater than a dielectric constant of the second material and a band gap of the first material is less than a band gap of the second material.
    Type: Application
    Filed: December 26, 2013
    Publication date: July 2, 2015
    Inventors: Sadasivan Shankar, MARK BOHR, Michael Haverty
  • Publication number: 20140264879
    Abstract: Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.
    Type: Application
    Filed: May 28, 2014
    Publication date: September 18, 2014
    Inventors: Kelin J. Kuhn, Kaizad Mistry, Mark Bohr, Chris Auth
  • Patent number: 8766372
    Abstract: Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: July 1, 2014
    Assignee: Intel Corporation
    Inventors: Kelin J. Kuhn, Kaizad Mistry, Mark Bohr, Chris Auth
  • Publication number: 20140077305
    Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
    Type: Application
    Filed: September 19, 2012
    Publication date: March 20, 2014
    Inventors: Abhijit Jayant Pethe, Tahir Ghani, Mark Bohr, Clair Webb, Harry Gomez, Annalisa Cappellani
  • Patent number: 8580679
    Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: November 12, 2013
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Sridhar Balakrishnan, Mark Bohr
  • Patent number: 8368171
    Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a metallic fuse structure by forming at least one via on a first interconnect structure, lining the at least one via with a barrier layer, and then forming a second interconnect structure on the at least one via.
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: February 5, 2013
    Assignee: Intel Corporation
    Inventors: Jose A. Maiz, Jun He, Mark Bohr
  • Publication number: 20120299069
    Abstract: Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.
    Type: Application
    Filed: August 7, 2012
    Publication date: November 29, 2012
    Applicant: Intel Corporation
    Inventors: Kelin J. Kuhn, Kaizad Mistry, Mark Bohr, Chris Auth
  • Patent number: 8258057
    Abstract: Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: September 4, 2012
    Assignee: Intel Corporation
    Inventors: Kelin J. Kuhn, Kaizad Mistry, Mark Bohr, Chris Auth
  • Patent number: 8174060
    Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: May 8, 2012
    Assignee: Intel Corporation
    Inventors: Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Mark Bohr