Patents by Inventor Mark Bohr

Mark Bohr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7422950
    Abstract: A MOS device comprises a gate stack comprising a gate electrode disposed on a gate dielectric, a first spacer and a second spacer formed on laterally opposite sides of the gate stack, a source region proximate to the first spacer, a drain region proximate to the second spacer, and a channel region subjacent to the gate stack and disposed between the source region and the drain region. The MOS device of the invention further includes a buried oxide (BOX) region subjacent to the channel region and disposed between the source region and the drain region. The BOX region enables deeper source and drain regions to be formed to reduce transistor resistance and silicide spike defects while preventing gate edge junction parasitic capacitance.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: September 9, 2008
    Assignee: Intel Corporation
    Inventors: Giuseppe Curello, Hemant V. Deshpande, Sunit Tyagi, Mark Bohr
  • Publication number: 20080213996
    Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
    Type: Application
    Filed: August 20, 2007
    Publication date: September 4, 2008
    Inventors: Valery M. Dubin, Sridhar Balakrishnan, Mark Bohr
  • Patent number: 7414298
    Abstract: The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: August 19, 2008
    Assignee: Intel Corporation
    Inventors: Shahriar Ahmed, Mark Bohr, Stephen Chambers, Richard Green
  • Publication number: 20080119016
    Abstract: Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual CNT's. The methods to fabricate three-dimensional carbon nanotube FET integrated circuits include the selective deposition of carbon nanotubes onto catalysts selectively formed on a conductive layer at the bottom of openings in a dielectric layer. The openings in the dielectric layer are formed using suitable techniques, such as, but not limited to, dielectric etching, and the formation of ring gate electrodes, including spacers, that provide openings for depositing self-aligned carbon nanotube semiconductor channels.
    Type: Application
    Filed: January 31, 2008
    Publication date: May 22, 2008
    Inventors: Valery Dubin, Mark Bohr
  • Publication number: 20080116439
    Abstract: A nano-electrode or nano-wire may be etched centrally to form a gap between nano-electrode portions. The portions may ultimately constitute a single electron transistor. The source and drain formed from the electrode portions are self-aligned with one another. Using spacer technology, the gap between the electrodes may be made very small.
    Type: Application
    Filed: November 8, 2007
    Publication date: May 22, 2008
    Inventors: Valery M. Dubin, Swaminathan Sivakumar, Andrew A. Berlin, Mark Bohr
  • Patent number: 7348675
    Abstract: Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual CNT's. The methods to fabricate three-dimensional carbon nanotube FET integrated circuits include the selective deposition of carbon nanotubes onto catalysts selectively formed on a conductive layer at the bottom of openings in a dielectric layer. The openings in the dielectric layer are formed using suitable techniques, such as, but not limited to, dielectric etching, and the formation of ring gate electrodes, including spacers, that provide openings for depositing self-aligned carbon nanotube semiconductor channels.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: March 25, 2008
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Mark Bohr
  • Publication number: 20080003746
    Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Giuseppe Curello, Ian R. Post, Chai-Hong Jan, Mark Bohr
  • Patent number: 7312155
    Abstract: A nano-electrode or nano-wire may be etched centrally to form a gap between nano-electrode portions. The portions may ultimately constitute a single electron transistor. The source and drain formed from the electrode portions are self-aligned with one another. Using spacer technology, the gap between the electrodes may be made very small.
    Type: Grant
    Filed: April 7, 2004
    Date of Patent: December 25, 2007
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Swaminathan Sivakumar, Andrew A. Berlin, Mark Bohr
  • Publication number: 20070273042
    Abstract: Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.
    Type: Application
    Filed: May 23, 2006
    Publication date: November 29, 2007
    Inventors: Kelin J. Kuhn, Kaizad Mistry, Mark Bohr, Chris Auth
  • Patent number: 7276801
    Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: October 2, 2007
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Sridhar Balakrishnan, Mark Bohr
  • Publication number: 20070138559
    Abstract: Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.
    Type: Application
    Filed: December 16, 2005
    Publication date: June 21, 2007
    Inventor: Mark Bohr
  • Publication number: 20070141798
    Abstract: A method for forming metal silicide layers in a high-k/metal gate transistor comprises forming a transistor with a sacrificial gate on a substrate, depositing a first ILD layer on the substrate, removing the sacrificial gate to form a gate trench, depositing a high-k dielectric layer within the gate trench, annealing the high-k dielectric layer, depositing a first metal layer within the gate trench, depositing a second ILD layer on the first ILD layer and the transistor, etching the first and second ILD layers to form a first contact trench and a second contact trench that extend down to a source region and a drain region of the transistor, depositing a second metal layer within the contact trenches, annealing the second metal layer to form metal silicide layers, and depositing a third metal layer within the first and second contact trenches to fill the contact trenches.
    Type: Application
    Filed: December 20, 2005
    Publication date: June 21, 2007
    Inventor: Mark Bohr
  • Publication number: 20070134859
    Abstract: A MOS device comprises a gate stack comprising a gate electrode disposed on a gate dielectric, a first spacer and a second spacer formed on laterally opposite sides of the gate stack, a source region proximate to the first spacer, a drain region proximate to the second spacer, and a channel region subjacent to the gate stack and disposed between the source region and the drain region. The MOS device of the invention further includes a buried oxide (BOX) region subjacent to the channel region and disposed between the source region and the drain region. The BOX region enables deeper source and drain regions to be formed to reduce transistor resistance and silicide spike defects while preventing gate edge junction parasitic capacitance.
    Type: Application
    Filed: December 14, 2005
    Publication date: June 14, 2007
    Inventors: Giuseppe Curello, Hemant Deshpande, Sunit Tyagi, Mark Bohr
  • Publication number: 20070132057
    Abstract: A semiconductor device and method for its fabrication are described. An active region spacer may be formed on a top surface of an isolation region and adjacent to a sidewall of an active region. In one embodiment, the active region spacer may suppress the formation of metal pipes in the active region.
    Type: Application
    Filed: December 8, 2005
    Publication date: June 14, 2007
    Inventors: Giuseppe Curello, Ian Post, Chia-Hong Jan, Sunit Tyagi, Mark Bohr
  • Publication number: 20070132034
    Abstract: A semiconductor device and method for its fabrication are described. An isolation body may be formed prior to formation of an active region. In one embodiment, the isolation body is void-free.
    Type: Application
    Filed: December 14, 2005
    Publication date: June 14, 2007
    Inventors: Giuseppe Curello, Mark Bohr, Hemant Deshpande, Sunit Tyagi
  • Patent number: 7208830
    Abstract: In one embodiment of the invention, an integrated circuit package includes an integrated circuit, a package substrate, a first bump, a second bump and a shunt to provide for current distribution and reliability redundancy. The first and second bumps provide a first and second electric current pathway between the integrated circuit and package substrate. The shunt provides a third electric current pathway between the first bump and the second bump.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: April 24, 2007
    Assignee: Intel Corporation
    Inventors: Mark Bohr, Jun He, Fay Hua, Dustin P. Wood
  • Patent number: 7202514
    Abstract: The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.
    Type: Grant
    Filed: April 17, 2003
    Date of Patent: April 10, 2007
    Assignee: Intel Corporation
    Inventors: Shahriar Ahmed, Mark Bohr, Stephen Chambers, Richard Green, Anand Murthy
  • Publication number: 20070069331
    Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a metallic fuse structure by forming at least one via on a first interconnect structure, lining the at least one via with a barrier layer, and then forming a second interconnect structure on the at least one via.
    Type: Application
    Filed: November 27, 2006
    Publication date: March 29, 2007
    Inventors: Jose Maiz, Jun He, Mark Bohr
  • Publication number: 20070034945
    Abstract: Optimal strain in the channel region of a PMOS transistor is provided by silicon alloy material in the junction regions of the device in a non-planar relationship with the surface of the substrate. The silicon alloy material, the dimensions of the silicon alloy material, as well as the non-planar relationship of the silicon alloy material with the surface of the substrate are selected so that the difference between the lattice spacing of the silicon alloy material and of the substrate causes strains in the silicon alloy material below the substrate surface, as well as above the substrate surface, to affect an optimal silicon alloy induced strain in the substrate channel. In addition, the non-planar relationship may be selected so that any strains caused by different lattice spaced layers formed over the silicon alloy material have a reduced effect on the strain in the channel region.
    Type: Application
    Filed: October 24, 2006
    Publication date: February 15, 2007
    Inventors: Mark Bohr, Tahir Ghani, Stephen Cea, Kaizad Mistry, Christopher Auth, Mark Armstrong, Keith Zawadzki
  • Publication number: 20070004123
    Abstract: Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventors: Mark Bohr, Steven Keating, Thomas Letson, Anand Murthy, Donald O'Neill, Willy Rachmady