Patents by Inventor Mark Carpenter Glass

Mark Carpenter Glass has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9946545
    Abstract: A loop buffer is provided with a main store 26 and an auxiliary store 28. The main store 26 stores micro-operation instructions. The auxiliary store 28 has fewer entries than the main store 26 and stores target addresses for predicted taken branch instructions stored within the main store 26. Read control circuitry serves to control reading from the main store and from an auxiliary store such that target addresses are read from the auxiliary store in association with the predicted taken branch instructions read from the main store.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: April 17, 2018
    Assignee: ARM Limited
    Inventors: James Nolan Hardage, Glen Andrew Harris, Mark Carpenter Glass
  • Publication number: 20150082007
    Abstract: A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.
    Type: Application
    Filed: November 20, 2014
    Publication date: March 19, 2015
    Inventors: Glen Andrew HARRIS, James Nolan HARDAGE, Mark Carpenter GLASS
  • Patent number: 8972701
    Abstract: A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilized for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: March 3, 2015
    Assignee: ARM Limited
    Inventors: James Nolan Hardage, Glen Andrew Harris, Mark Carpenter Glass
  • Patent number: 8914615
    Abstract: A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: December 16, 2014
    Assignee: ARM Limited
    Inventors: Glen Andrew Harris, James Nolan Hardage, Mark Carpenter Glass
  • Publication number: 20130145127
    Abstract: A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilised for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 6, 2013
    Applicant: ARM LIMITED
    Inventors: James Nolan Hardage, Glen Andrew Harris, Mark Carpenter Glass
  • Publication number: 20130145126
    Abstract: A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Applicant: ARM LIMITED,
    Inventors: Glen Andrew Harris, James Nolan Hardage, Mark Carpenter Glass
  • Publication number: 20120124301
    Abstract: A loop buffer is provided with a main store 26 and an auxiliary store 28. The main store 26 stores micro-operation instructions. The auxiliary store 28 has fewer entries than the main store 26 and stores target addresses for predicted taken branch instructions stored within the main store 26. Read control circuitry serves to control reading from the main store and from an auxiliary store such that target addresses are read from the auxiliary store in association with the predicted taken branch instructions read from the main store.
    Type: Application
    Filed: November 16, 2010
    Publication date: May 17, 2012
    Applicant: ARM LIMITED
    Inventors: James Nolan Hardage, Glen Andrew Harris, Mark Carpenter Glass