Abstract: A method is provided for fairly allocating bandwidth to a plurality of devices connected to a communication link implemented as a plurality of point-to-point links. The point-to-point links interconnect the devices in a daisy chain fashion. Each device is configured to transmit locally generated packets and to forward packets received from downstream devices onto one of the point-to-point links. The rate at which each device transmits local packets relative to forwarding received packets is referred to as the device's insertion rate. A fair bandwidth allocation algorithm is implemented in each (upstream) device to determine the highest packet issue rate of the devices which are downstream of that (upstream) device. The packet issue rate of a downstream device is the number of local packets associated with the downstream device that are received at the upstream device relative to the total number of packets received at the upstream device.

Abstract: A method for implementing interrupt requests in a computing system comprising a plurality of processing devices interconnected by a plurality of point-to-point links is provided. An interrupt request is broadcast on the point-to-point links to each of the plurality of processing devices. Each processing device is configured to decode the interrupt request to determine whether the processing device is a target of the interrupt request. Each processing device transmits a response to acknowledge receipt of the interrupt request, regardless of whether the processing device is a target of the interrupt request. If the interrupt request is an arbitrated request, each processing device also is configured to respond to the interrupt request with priority information. A processing device is then selected to service the arbitrated request based on the priority information.

Abstract: A method of assigning priorities and resolving bus contention in a distributed computer system is disclosed. Each system node is assigned an identifier. Priorities are reassigned at each change in bus access such that the node that most recently had access to the bus is assigned the lowest priority with the node having the next identifier in sequence being assigned the highest priority and all other nodes assigned priority in accordance with their identifier's position in the sequence. The identifiers are logically treated as organized in a circular fashion such that the lowest node identifier is considered to come next in the sequence after the highest node identifier.

Abstract: Apparatus and method is disclosed for controlling the timing of the addressing, fetching and executing of microinstructions in a data processing system such that delayed sequencing microinstructions, stretched delayed sequencing microinstructions and immediate sequencing microinstructions may be intermixed in the microinstruction stream. Circuitry is provided to determine the type of sequencing specified for each microinstruction and control the generation of the execution cycle signal and the microinstruction address clocking signal such that these signals occur in the appropriate time sequence to accomplish the specified sequencing.

Abstract: A data processing uses instructions which may refer to operands in main memory by either physical or logical addresses. The central processor has an internal memory organized as two portions. The first portion provides a scratchpad memory function for the central processor and the second portion is responsive to logical addresses to provide corresponding physical addresses.