Abstract: The disclosed embodiments relate to a system and method for processing a video signal, comprising assigning pixels from a set of pixels to at least one of a plurality of bins based on a brightness level associated with each pixel of the set of pixels, each of the plurality of bins containing pixels having a brightness level above or below a specified value, and identifying a coarse horizon value corresponding to a first one of the bins that includes a number of pixels corresponding to a brightness level.

Abstract: Present embodiments are directed to a system and method for correcting video image distortion in a video system. An exemplary embodiment includes steps or features for retrieving baseline measurements for set portions of a display area, wherein the baseline measurements take into account distortions detected in the video system. Further, the exemplary embodiment includes determining stretch coefficients for the set portions of the display area, retrieving an image corresponding to the display area, and correcting positioning of a plurality of pixels of the image based on the baseline measurements and the stretch coefficients.

Abstract: The disclosed embodiments relate to a system and method that enhance contrast ratio of a display device using asymmetrically delayed illumination signal control. An exemplary embodiment comprises determining a pixel brightness level for a video frame, and delaying application of the illumination signal based on a change of the pixel brightness level.

Abstract: The disclosed embodiments relate to a system and method of enhancing a contrast ratio of a display device. An exemplary method comprises determining a quantity of pixels in a frame of video data having a predetermined level of blackness, comparing the quantity of pixels to a reference value, and modulating an illumination signal based on a quantity of pixels exceeding the reference value.

Abstract: Efficient re-sampling within a memory occurs by first generating an address request that contains a first portion that identifies a selected data string of interest, and a second portion that identifies a particular group of data values within the selected string. The first portion of the address request is applied to the memory to obtain the selected string of values during a single read operation. The second portion of the read address serves to mask the selected string of values to obtain the particular group of values of interest within the string.

Abstract: A system such as an audio and/or video system includes a multiplexed analog-to-digital converter arrangement. The arrangement includes an ADC for converting first and second analog signals to first and second digital signals, respectively, and for outputting the first digital signal during a first time interval and outputting the second digital signal during a second time interval. A digital filter is provided for filtering the first and second digital signals to generate first and second filtered signals, respectively, and for outputting the first and second filtered signals in a time-aligned manner during a third time interval.

Abstract: A method (400) and a system (100) for providing video signals to video displays includes the steps of receiving at least one input video signal (150), dithering the non-uniformity color correction (445), applying the non-uniformity color correction to the input video signal to generate a color corrected video signal (450), and increasing a frame rate of the color corrected video signal (120). Gamma correction (125) can be applied to the color correction. Generating a dithered non-uniformity color correction can include selecting from a data storage (115) a plurality of RGB correction matrices (300), measuring at least one brightness level of the input video signal, selecting for the picture level correction a first RGB correction matrix if the brightness is within a first range of values (425), a second RGB correction matrix if the brightness is within a second range of values (435), and interpolating (440) the plurality of RGB correction matrices if the brightness is within a third range of values.

Abstract: A digital and analog television signal digitization and processing device that performs the digitization and processing functions using a common reference frequency source that is used to generate multiple subclock signals, wherein the reference frequency source is independent of any synchronizing characteristic of the input signal. For dual channel analog signal processing, the common frequency source is not locked to either channel/input signal. Digital signal processing is accomplished based on the same common reference frequency source. Advantageously, the present invention allows all of the analog-to-digital converters and decoder circuitry/logic necessary for simultaneously digitizing and processing several analog and digital television signals to be integrated on a single integrated circuit as well as eliminating duplicate frequency generation circuits.

Abstract: An ACC system includes a controllable amplifier having an input coupled to receive a chroma input signal and an output for providing an chroma output signal of controllable amplitude. A first feedback path, including a cascade connection of means for providing a signal representative of a measured burst amplitude, means for providing an error signal representative of the difference between a desired burst amplitude and the measured burst amplitude, and an integrator, is coupled between the output of the controllable amplifier and a gain control input of the controllable amplifier.

Abstract: A digital video system includes a sample rate converter and an inverse-sample rate converter. The sample rate converter converts video data from a non-orthogonal pixel domain to an orthogonal pixel domain. The inverse-sample rate converter converts the video data from the orthogonal pixel domain to the non-orthogonal pixel domain. The inverse sample rate converter utilizes a timing signal generated by the sample rate converter when converting the video data from the orthogonal pixel domain to the non-orthogonal pixel domain.

Abstract: A system (400) such as an audio and/or video system includes a multiplexed analog-to-digital converter (“ADC”) arrangement (500). The arrangement (500) includes an ADC (530) for converting first and second analog signals to first and second digital signals, respectively, and for outputting the first digital signal during a first time interval and outputting the second digital signal during a second time interval. A digital filter (550) is provided for filtering the first and second digital signals to generate first and second filtered signals, respectively, and for outputting the first and second filtered signals in a time-aligned manner during a third time interval.

Abstract: A method (400) and a system (100) for providing video signals to video displays includes the steps of receiving at least one input video signal (150), dithering the non-uniformity color correction (445), applying the non-uniformity color correction to the input video signal to generate a color corrected video signal (450), and increasing a frame rate of the color corrected video signal (120). Gamma correction (125) can be applied to the color correction. Generating a dithered non-uniformity color correction can include selecting from a data storage (115) a plurality of RGB correction matrices (300), measuring at least one brightness level of the input video signal, selecting for the picture level correction a first RGB correction matrix if the brightness is within a first range of values (425), a second RGB correction matrix if the brightness is within a second range of values (435), and interpolating (440) the plurality of RGB correction matrices if the brightness is within a third range of values.

Abstract: A video system (100) includes detection circuitry (200A-200C) operative to detect pseudo-synchronization pulses within a composite synchronization signal in dependence upon at least one timing signal. Timing circuitry (200D-200F) is operative to generate the at least one timing signal without utilizing synchronization information within the composite synchronization signal.

Abstract: A video system (100) includes a chrominance processing arrangement (200). The chrominance processing arrangement (200) includes a burst accumulator (240) operative to detect a polarity inversion within a burst interval associated with a horizontal line of video information, and generate at least one output signal that compensates for the detected polarity inversion.

Abstract: A digital video system includes a sample rate converter and an inverse-sample rate converter. The sample rate converter converts video data from a non-orthogonal pixel domain to an orthogonal pixel domain. The inverse-sample rate converter converts the video data from the orthogonal pixel domain to the non-orthogonal pixel domain. The inverse sample rate converter utilizes a timing signal generated by the sample rate converter when converting the video data from the orthogonal pixel domain to the non-orthogonal pixel domain.

Abstract: Interface apparatus for interfacing data to a plurality of different clock domains where the clock signals in the different domains are phase locked together and respective clock signals have different frequencies includes a plurality of cascade connected first and second latches coupled between respective clock domains. One of the latches is a clocked Data Latch and the other is a clocked and Enabled Data Latch. A timing generator provides respective domain clock signals, wherein a domain clock signal of a domain providing a data signal is applied to the clock input connection of the first latch of a respective cascade connected set of latches and a domain clock signal of a domain receiving said data signal is applied to the second latch. The timing generator also provides a common Enable Signal phase locked to the domain clocked signals. The common Enable Signal is applied to the enable input terminal of one of the latches of each set of cascade connected latches.

Abstract: An ACC system includes a controllable amplifier having an input coupled to receive a chroma input signal and an output for providing an chroma output signal of controllable amplitude. A first feedback path, including a cascade connection of means for providing a signal representative of a measured burst amplitude, means for providing an error signal representative of the difference between a desired burst amplitude and the measured burst amplitude, and an integrator, is coupled between the output of the controllable amplifier and a gain control input of the controllable amplifier.

Abstract: A source (20) provides an input signal (S1) to be phase shifted and a combining circuit (24) concurrently combines first (A), second (B) and third (C) intermediate signals derived from the input signal (S1), and having differing phase shifts (0, −45, +135 deg), to form a phase shifted output signal (S2). A first amplitude controller (34, 38, 30, 32), responsive to a phase control signal (S3) supplied thereto, varies the amplitudes of the second (B) and third (C) intermediate signals in opposite directions (38) for controlling the phase of the phase shifted output signal. Additionally, a further amplitude controller (40, 42) is provided for reducing a tendency for variations in the phase shift control signal (S3) to alter the amplitude of alternating current (FIG. 5) and direct current (FIG. 6) components of the phase shifted output signal (S2).

Abstract: Adaptive comb filter circuitry is responsive to chrominance vector absolute values to inhibit hanging dots. Chrominance vector absolute values are calculated by delaying bandpass filtered video signal to concurrently provide a plurality of sample absolute values. The plurality of sample absolute values are weighted and summed. The maximum and the minimum of the plurality of sample absolute values are selected and respectively weighted. The weighted maximum and minimum are combined with the sum of weighted samples to provide approximated chrominance vector absolute values. Exemplary circuitry is illustrated which develop real time chrominance vector magnitude values within 1.5-% p-p error. The vector magnitude approximation circuitry may be used for calculating vectors represented by successive samples which do not have an orthogonal relationship.

Abstract: Analog to digital converters with enhanced performance in the presence of clock noise interference are configured with sampling clock phase selection circuitry to enable operation of the converter at the optimum sampling time intervals with respect to the interfering noise. The selection circuitry includes apparatus for generating a plurality of sampling clock phases and a multiplexer coupled to the plurality of phases to select the optimum clock phase.