Abstract: A self-testing smart memory (28) is provided in which memory test circuitry (46) within the smart memory (28) writes a pattern to a data RAM (32) and a broadcast RAM (34) and then reads the data RAM (32) and the broadcast RAM (34) to determine if any failures exist within the memory locations. Furthermore, a data path tester (50) determines the functionality of a data path (30) within smart memory (28).

Abstract: A self-testing smart memory (28) is provided in which memory test circuitry (46) within the smart memory (28) writes a pattern to a data RAM (32) and a broadcast RAM (34) and then reads the data RAM (32) and the broadcast RAM (34) to determine if any failures exist within the memory locations. Furthermore, a data path tester (50) determines the functionality of a data path (30) within smart memory (28).

Abstract: The device hereof provides an integrated circuit resistor (34) comprising amorphous or noncrystalline semiconducting material. Further advantages can be gained in area by forming the noncrystalline semiconductor resistor in a non-planar fashion (i. e. with a vertical construction) wherein a first electrical contact is made to the resistor on its bottom surface and a second electrical contact is made to the resistor on its top surface.Other devices, systems and methods are also disclosed.

Abstract: Memory chips with data memory (202), embedded logic (206) and broadcast memory (204) for two modes of operation are disclosed. A first mode of operation is the usual memory mode expected of a data RAM. The second mode of operation allows localized computation and/or processing of the data in data memory (202) by the embedded logic (206) with minimal handshaking with a remote CPU. In a functioning system, the memory chips are organized in a hierarchical manner and include address-associative memory systems.

Abstract: A logic module 400 for use in a field programmable gate array 100 can be selectively reconfigured to perform over 2,200 boolean combinational functions on output 431, to operate as a full adder with sum and carry outputs, or to perform the sequential function of a D latch or a D flipflop. Logic module 400 is comprised of 2-input multiplexers 500 and 600 which are used to form both the combinational and sequential circuits, thereby efficiently utilizing space on gate array 100.

Abstract: A device is disclosed which combines the advantages of CMOS and bipolar using an existing parasitic bipolar device. As such high on-chip density is attainable with the device along with high speed capability while maintaining low power advantages.

Abstract: The device hereof provides an integrated circuit resistor (34) comprising amorphous or noncrystalline semiconducting material. Further advantages can be gained in area by forming the noncrystalline semiconductor resistor in a non-planar fashion (i. e. with a vertical construction) wherein a first electrical contact is made to the resistor on its bottom surface and a second electrical contact is made to the resistor on its top surface.Other devices, systems and methods are also disclosed.

Abstract: An adder-based base cell (10) is provided for field programmable gate arrays. The base cell (10) includes a first inverter (13) operable to receive a first input signal (A). A first NAND gate (12) is coupled to the first inverter (13) and is operable to receive a second input signal (B). A first 2:1 multiplexer (14) is coupled to the first NAND gate (12) and is operable to receive a third input signal (C). The output of the first 2:1 multiplexer (14) represents a first function (F1). A second inverter (17) is operable to receive a fourth input signal (D). A second NAND gate (16) is coupled to the second inverter (17) and is operable to receive a fifth input signal (E). An XOR gate (18) is coupled to the second NAND gate (16), is operable to receive a sixth input signal (F), and is coupled to the first 2:1 multiplexer (14). The output of the XOR gate represents a partial sum function (PS.sub.-- 1).

Abstract: The described embodiments of the present invention provide an apparatus and method for rapidly programming field programmable devices. A dummy antifuse is provided on the field programmable device for testing prior to actual programming. The current drawn by the device is measured by the programming apparatus until an adequate soaking current is measured while programming the test antifuse. The programming apparatus then records the time required this current level and selects that time as the programming period T.sub.p. This programming time T.sub.p is then used to program the entire device. T.sub.p is now the minimum time required given the process variations of this particular device to adequately program the antifuses which must be blown.

Abstract: An integrated electronic circuit architecture has low leakage current and capacitance and includes a user-programmable integrated circuit design (110) having a plurality of designed conductors (112, 118) and a plurality of designed functional circuit blocks (e.g., 12,14, etc.). In the architecture, a plurality of user-programmable antifuse elements (e.g., 26, 28, 30, etc.) connect to the plurality of conductors (112, 118) and the plurality of functional circuit blocks (12, 14, 16, etc.). The plurality of user-programmable antifuse elements (e.g., 26, 28, 30, etc.) connect the plurality of conductors (112, 118) with one another and to the plurality of functional circuit blocks (12, 14, 16, etc.). The plurality of conductors (112, 118) is segregated into at least two groups including a first group of conductors and a second group of conductors.

Abstract: Programmable circuitry (10) is provided including a plurality of logic modules (12) each having at least one input conductor (16). A nearest neighbor conductor (36) is fusibly coupled to output circuitry (25) of a selected logic module (12), the nearest neighbor conductor (36) intersecting the input conductor (16) of a nearest neighbor logic module (12). A fuse (40) disposed at the intersection of the nearest neighbor conductor (36) and the input conductor (16) of the nearest neighbor logic module (12) is provided for selectively establishing electrical coupling therebetween.

Abstract: A memory cell (10) comprising a first antifuse (A1) operable to place the memory cell (10) in a non-volatile state. In one embodiment, the memory cell (10) comprises a pair of cross-coupled inverters (I1,I2). The first antifuse (A1)is connected between an output (B) of one of the cross-coupled inverters and ground and is operable to place the memory cell in a first non-volatile state. A second antifuse (A2) is connected between an output (B) and a supply voltage (Vcc) and is operable to place the memory cell (10) in a second non-volatile state. Only one of the antifuses, (A1 or A2) is programmed in memory cell (10).

Abstract: An improved memory cell (118) is provided which may be incorporated into an array (202) of memory cells. Array (202) includes a first gate conductor region (224) and a second gate conductor region (238), wherein the first and second gate conductor regions are orthogonal to one another. Each one-half of the cell may include two series transistors connected to a cross-coupled trench transistor. Cross-coupling of the trench transistors is effected through the use of parallel local interconnect regions (256) and (258).

Abstract: An improved memory cell 118 is provided utilizing transistor pairs 142, 144 ands 160, 162 as dual purpose transistor pairs for the two modes of operation of the cell. During the first or non-access mode of operation, the transistor pairs operate as switched capacitive elements in order to provide an equivalent resistance between bit line 140 and first node 26 and inverted bit line 158 and second node 130. Control circuit 119 maintains bit lines 140 and inverted bit line 158 high during this non-access mode. During the second or access mode of operation, each transistor pair operates as a respective pass transistor for connecting bit line 140 to first node 126 and inverted bit line 158 to second node 130 so that data may be read from, or written to, the cross-coupled transistors 120 and 122.