Abstract: In accordance with a first aspect of the present disclosure, a system is provided for applying patches to executable codes, comprising: a plurality of execution environments configured to execute said codes in different execution contexts; a control unit configured to apply the patches to said codes; wherein the control unit is configured to apply a specific patch to a specific code upon or after an execution environment configured to execute said specific code switches to an execution context corresponding to said specific code. In accordance with other aspects of the present disclosure, a corresponding method is conceived for applying patches to executable codes, and a corresponding computer program is provided.

Abstract: In accordance with a first aspect of the present disclosure, a system is provided for applying patches to executable codes, comprising: a plurality of execution environments configured to execute said codes in different execution contexts; a control unit configured to apply the patches to said codes; wherein the control unit is configured to apply a specific patch to a specific code upon or after an execution environment configured to execute said specific code switches to an execution context corresponding to said specific code. In accordance with other aspects of the present disclosure, a corresponding method is conceived for applying patches to executable codes, and a corresponding computer program is provided.

Abstract: A secure element operating in conjunction with a secure partition of a system-on-a-chip (SoC) having set top box (STB) functionality allows for digital rights management (DRM) key handling in a mobile platform. The secure element can include a secure processing system (SPS) to be implemented as a hard macro, thereby isolating the SPS from a peripheral processing system (PPS). The secure element and the secure partition of the SoC may be operatively connected by a secure cryptographic channel.

Abstract: A secure element operating in conjunction with a secure partition of a system-on-a-chip (SoC) having set top box (STB) functionality allows for digital rights management (DRM) key handling in a mobile platform. The secure element can include a secure processing system (SPS) to be implemented as a hard macro, thereby isolating the SPS from a peripheral processing system (PPS). The secure element and the secure partition of the SoC may be operatively connected by a secure cryptographic channel.

Abstract: A method includes testing, by a processor, a secure portion of a semiconductor device through a first interface between the processor and the semiconductor device; and sending, by the processor, a pass or fail indication of a result of the testing of the secure portion of the semiconductor device to the tester through a second interface between the processor and the tester.

Abstract: An integrated circuit accesses first encrypted data stored in an external random access memory and accesses second encrypted data stored in an external read-only memory. The external random access memory and the external read-only memory are external to the integrated circuit. When accessing a first portion of the first encrypted data stored in the external random access memory, a first algorithm is used to decrypt the first portion of the first encrypted data. When accessing a first portion of the second encrypted data stored in the external read-only memory, a second algorithm is used to decrypt the first portion of the second encrypted data. The second algorithm is different than the first algorithm.

Abstract: An integrated circuit includes secure logic that requires protection. Secure assurance logic protects the secure logic. The secure assurance logic includes a plurality of protection modules that monitor the occurrence of insecure conditions. Each protection module monitors a different type of insecure condition. Each protection module asserts an alarm signal when an associated insecure condition is detected. The alarm signals asserted by the plurality of protection modules are stored.

Abstract: A computing system, includes a processor, a cache, a memory system, and a secure cache controller system. The cache stores a plurality of cache lines. The memory system stores a plurality of blocks of encrypted data. The secure cache controller system is situated between the memory system and the cache. When there is a miss of a first cache line of data in the cache and the first cache line of data resides in a first block of encrypted data within the memory system, the secure cache controller system fetches the first block of encrypted data, decrypts the first block of encrypted data and forwards the first cache line to the cache.

Abstract: Logic circuitry performs a matching algorithm function. A memory produces a match signal that indicates which memory cells contain data that matches input address data to the memory. A first logic AND function performs a logic AND between a current value of the match signal currently produced by the memory for the input address data with a prior value of the match signal produced by an immediately prior input address data. A buffer holds index data. A second logic AND function compares output of the first logic AND function with the index data. Output of the second logic AND function is returned to the buffer as new index data. Index logic generates an offset based on the index data stored in the buffer. A send byte function asserts a send byte signal when the match signal is zero and when the output of the second logic AND function is zero. A length counter is incremented for every cycle in which the send byte signal is not asserted.

Abstract: An address decoder includes a plurality of address decoder modules. Each address decoder module has a select line for each of a plurality of devices. Each of a plurality of XOR combination circuits performs a logic XOR function of all select lines for a single device from the plurality of devices. State control within the address decoder activates one address decoder module at a time.

Abstract: Power-on-reset logic is included within an integrated circuit. The power-on-reset logic includes a power-on-reset cell. The power-on-reset cell causes a reset signal to be issued upon a power signal being connected to the integrated circuit. The power-on-reset cell includes a power down input connected to a power-down line. When a power-down signal is placed on the power-down line, the power-on-reset cell is inactivated so that the power-on-reset cell does not cause the reset signal to be issued upon the power signal being connected to the integrated circuit. The power-on-reset logic also includes a logic block connected to the power-down line and to a system clock. The logic block issues a reset when the power-down signal is placed on the power-down line and the system clock is active. For example, the logic block is a delay (D) flip-flop having a D input connected to the power down line and a clock input connected to the system clock.

Abstract: In accordance with the preferred embodiment of the present invention, a first-in-first out queue includes a buffer for storing data. A write pointer indicates a next position for data to be written into the buffer from an external interface. An input pointer indicates a next position for data to be read out to processing circuitry. An output pointer indicates a next position for data which has been processed by the processing circuitry to be returned to the buffer. A read pointer indicates a next position for data to be read out of the buffer to the external interface.

Abstract: An over frequency detection circuit which is based on the concept of a critical path in a design to protect an IC chip from running at a rate which will produce unpredictable results. The over frequency detection circuit will compare the output of a critical path generation circuit with that of a known path generation circuit. The known path generation circuit must have a delay which is guaranteed to be much shorter than the delay of the critical path generation circuit. If the output of the critical path generation circuit is not the same as the output of the known path generation circuit, then the critical path generation circuit has begun to fail and the IC chip should be disabled.

Abstract: To perform a secure operation, an original encrypted value is obtained from a memory. The original encrypted value is decrypted to obtain an original value and an original validity code. The original validity code is compared with a stored validity code. If the original validity code is equivalent to the stored validity code, the secure operation is performed on the original value to produce a new value. Then a permanent alteration is made to the stored validity code to produce a new stored validity code. The new value and the new stored validity code are encrypted to produce a new encrypted value. The new encrypted value is stored in the memory.

Abstract: A hardware implementation of a hashing algorithm is presented. In a first pipeline stage, a first memory stores input data for the hashing algorithm. Data is selected out of the first memory, for example, using a counter which is reset and incremented by differing values depending upon the round of the algorithm. A second memory stores constants used for the hashing algorithm. Constants are selected out of the second memory, for example, using a counter. An adder adds data from the first memory and a constant from the second memory with a state value selected, for example, using a multiplexer. The result is stored as an intermediate algorithm value in a first pipeline register. In a second pipeline stage a second adder adds one of a plurality of hashing function values to the intermediate algorithm value in the first pipeline register. The result is shifted. A third adder adds the shifted result to one of the plurality of state values and places the result into a second pipeline register.

Abstract: High-speed multiplication and exponentiation are performed by performing a modulus multiplication operation on received operands. A memory stores the operands and intermediate mathematical operation results of the modulus multiplication operation. A software-controllable, hardware state machine controls performance of the modulus multiplication operation according to a Montgomery multiplication algorithm.

Abstract: A circuit on a detachable device, such as a plug-in card, determines when the detachable device has been disconnected from a host device. The circuit includes a node, a power source, a switch and a control circuit. The node is connected to ground when the detachable device is connected to the host device. The node is disconnected from ground when the detachable device is disconnected from the host device. The switch is for connecting and disconnecting the node to the power source. The control circuit is for, repeatedly at a predetermined interval of time while the detachable device remains connected to the host device, causing the switch to connect the node to the power source for a first length of time. The control circuit, at the end of the first length of time, checks a voltage level of the node in order to detect whether the detachable device has been disconnected from the host device.

Abstract: An integrated circuit accesses encrypted data stored in an external memory, the integrated circuit includes a main memory for storing decrypted data. A processor within the integrated circuit utilizes the decrypted data in the main memory. A soft secure memory management unit (SMMU), within the integrated circuit, monitors data accesses by the processor. The soft SMMU signals the processor when the processor attempts to access first data which is not within the decrypted data in the main memory but is within the encrypted data stored in the external memory. When the soft SMMU signals the processor, the processor oversees transfer of the first data from the external memory and oversees decryption of the first data.

Abstract: A digital standard cell implemented ring oscillator circuit for placement within an integrated circuit device. In one embodiment, the digital standard cell ring oscillator circuit is used in conjunction with a system for generating non-deterministic (e.g., random) output signals which can be used for data encryption. A random number generator circuit is used within the above system and the standard cell ring oscillator of the present invention is used to provide oscillator signals to different frequency legs of the random number generator circuit and can also be used to supply a jitter clock. The timing characteristics (e.g., frequency) of the standard cell ring oscillator vary with its fabrication process, its fabrication environment, and the temperature when used; timing characteristics are therefore unpredictable from "chip" to "chip" and from one point in time to another with respect to the same "chip." This increases the non-deterministic properties of the random number generator.

Abstract: A system clock signal monitor that monitors a system clock signal by comparing a pulse width of a logic high pulse and a pulse width of a logic low pulse of each system clock duty cycle of the system clock signal to one or more reference clock duty cycles in order to detect any pulse width violations. For each system clock duty cycle, a pulse width violation is detected if the pulse width of a logic high pulse and/or the pulse width of a logic low pulse is equal to or greater than a maximum time interval for the logic high pulse and the logic low pulse. A pulse width violation may also occur if the pulse width of a logic high pulse and/or the pulse width of a logic low pulse is within a risk range (as defined by the system designer) of the maximum time interval for the logic high pulse and the logic low pulse. The system clock signal monitor can be further designed to warn/reset a processor or a user of the processor upon the detection of one or more detected occurrences of a pulse width violation.