Patents by Inventor Mark M. Tehranipoor

Mark M. Tehranipoor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230394645
    Abstract: Various embodiments provide computer vision techniques for ensuring system- and component-level integrity via component characterization. Various embodiments may comprise computer vision systems that are configured to extract pin information from surface-mount device (“SMD”) contours. Accordingly, the disclosed embodiments may include a computer vision system configured to detect the extremities of each pin in a SMD contour image based on a combination of at least one of machine learning and one or more PCB image collection datasets.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 7, 2023
    Inventors: Navid Asadi-Zanjani, Mark M. Tehranipoor, Nathan Jessurun, Jacob C. Harrison
  • Patent number: 11799673
    Abstract: Combined physical unclonable function (PUFs); methods, apparatuses, systems, and computer program products for enrolling combined PUFs; and methods, apparatuses, systems, and computer program products for authenticating a device physically associated with a combined PUF are described. In an example embodiment, a combined PUF includes a plurality of PUFs and one or more logic gates. Each PUF includes a plurality of stages and an arbiter configured to generate a single PUF response based on response portions generated by the plurality of stages. The one or more logic gates are configured to combine the single PUF response for each of the plurality of PUFs in accordance with a combination function to provide a combined response.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: October 24, 2023
    Assignees: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INCORPORATED, TECHNISCHE UNIVERSITAET BERLIN
    Inventors: Fatemeh Ganji, Shahin Tajik, Jean-Pierre Seifert, Domenic Forte, Mark M. Tehranipoor
  • Patent number: 11704415
    Abstract: Methods, apparatus and computer program product for protecting a confidential integrated circuit design process.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: July 18, 2023
    Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INCORPORATED
    Inventors: Mark M. Tehranipoor, Andrew C. Stern, Adib Nahiyan, Farimah Farahmandi, Fahim Rahman
  • Publication number: 20230179434
    Abstract: Combined physical unclonable function (PUFs); methods, apparatuses, systems, and computer program products for enrolling combined PUFs; and methods, apparatuses, systems, and computer program products for authenticating a device physically associated with a combined PUF are described. In an example embodiment, a combined PUF includes a plurality of PUFs and one or more logic gates. Each PUF includes a plurality of stages and an arbiter configured to generate a single PUF response based on response portions generated by the plurality of stages. The one or more logic gates are configured to combine the single PUF response for each of the plurality of PUFs in accordance with a combination function to provide a combined response.
    Type: Application
    Filed: April 7, 2020
    Publication date: June 8, 2023
    Applicant: Technische Universitaet Berlin
    Inventors: Fatemeh Ganji, Shahin Tajik, Jean-Pierre Seifert, Domenic Forte, Mark M. Tehranipoor
  • Patent number: 11611429
    Abstract: Methods and integrated circuit architectures for assuring the protection of intellectual property between third party IP providers, system designers (e.g., SoC designers), fabrication entities, and assembly entities are provided. Novel design flows for the prevention of IP overuse, IP piracy, and IC overproduction are also provided. A comprehensive framework for forward trust between 3PIP vendors, SoC design houses, fabrication entities, and assembly entities can be achieved, and the unwanted modification of IP can be prevented.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: March 21, 2023
    Assignees: University of Florida Research Foundation, Incorporated, The University of Connecticut
    Inventors: Mark M. Tehranipoor, Domenic J. Forte, Ujjwal Guin
  • Patent number: 11604912
    Abstract: Embodiments of the present disclosure provide methods, apparatus, systems, computing devices, computing entities for setting deprocessing parameters used in conducting hardware deprocessing on a hardware.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: March 14, 2023
    Assignee: University of Florida Research Foundation, Incorporated
    Inventors: Mark M. Tehranipoor, Navid Asadi-Zanjani, Olivia Pauline Paradis, Nitin Varshney
  • Patent number: 11520967
    Abstract: There is a need for more effective and efficient printed circuit board (PCB) design. This need can be addressed by, for example, solutions for performing automated PCB component estimation. In one example, a method includes identifying a plurality of initial component estimations for the PCB; performing a shadow detection segmentation using the plurality of initial component estimations, a non-direct-lighting image, and one or more direct-lighting images to generate a first set of detected PCB components; performing a super-pixel segmentation using the plurality of initial component estimations and the non-direct-lighting-image to generate a second set of detected PCB components; and generating a bill of materials for the PCB based at least in part on the first set of detected PCB components and the second set of detected PCB components.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: December 6, 2022
    Assignee: University of Florida Research Foundation, Incorporated
    Inventors: Navid Asadi-Zanjani, Nathan Jessurun, Mark M. Tehranipoor, Olivia Pauline Paradis
  • Patent number: 11508857
    Abstract: A pyramid structure to mitigate optical probing attacks in ICs by scrambling the measurements reflected by a laser pulse is disclosed. The pyramid structure is applied to selected areas at the bottom surface of the metal traces in metal layer to circumvent the extra silicon layer and thus minimize the changes to the conventional device structures. The pyramid structure includes randomized pyramids at nanometer scale. Optical simulation results show the pyramidized metal surface is able to prevent optical probing attacks. The fabrication of pyramids is CMOS compatible as well. Optical simulations are performed to analyze the impact these nano-scaled pyramids in a laser voltage probing attacking model. The nanopyramid can disturb the optical measurements enough to make the attacks practically infeasible. In addition, the nanopyramid structure countermeasure works in a passive mode without consuming any energy.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: November 22, 2022
    Assignee: University of Florida Research Foundation, Incorporated
    Inventors: Haoting Shen, Navid Asadizanjani, Domenic J. Forte, Mark M. Tehranipoor
  • Patent number: 11475168
    Abstract: Various examples are provided related to power side-channel vulnerability assessment. In one example, a method includes identifying target registers in an IC design; generating input patterns associated with a target function that can generate a power difference in the target registers when processing the target function; determining a side-channel vulnerability (SCV) metric using the power difference produced by the input patterns; and identifying a vulnerability in the IC design using the SCV metric. Identification of the vulnerability allows for modification of the IC design at an early stage, which can avoid power side-channel attacks (e.g., DPA and CPA) in the fabricated IC design. The method can be used for pre-silicon power side-channel leakage assessment of IC designs such as, e.g., cryptographic and non-cryptographic circuits.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: October 18, 2022
    Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC.
    Inventors: Mark M. Tehranipoor, Adib Nahiyan, Domenic J. Forte, Jungmin Park
  • Publication number: 20220180003
    Abstract: Various embodiments provide methods, systems, computer program products, apparatuses, and/or the like for assessing vulnerability of an IC design to fault injection attacks, such as through a security property-driven vulnerability assessment framework for efficiently evaluating faults with respect to certain security properties associated with the IC design. In one embodiment, a method is provided. The method includes generating, using a fault-injection technique specification, one or more fault models describing attributes of one or more faults. The method further includes selecting, using the fault models and executable security properties associated with a design file of an IC design, a fault list identifying a plurality of possible faults for the IC design. The method further includes identifying, based at least in part on performing a fault simulation on the design file with the fault list, critical locations of the IC design.
    Type: Application
    Filed: December 3, 2021
    Publication date: June 9, 2022
    Inventors: Mark M. TEHRANIPOOR, Farimah FARAHMANDI, Huanyu WANG
  • Publication number: 20220130031
    Abstract: Embodiments of the present disclosure provide methods, apparatus, systems, and computer program products for using an image of an integrated circuit (IC) including a plurality of cells to locate one or more target cells within the IC. Accordingly, in various embodiments, a footprint for each cell of the plurality of cells is encoded to transform the image of the IC into a two-dimensional string matrix. A string search algorithm is then applied on each encoded dopant region found in the two-dimensional string matrix using an encoded target layout cell to identify one or more candidate regions of interest within the image. Finally, a mask window is slid over each candidate region of interest while performing matching using match criteria to identify any target cells in the one or more target cells that are located within the candidate region of interest.
    Type: Application
    Filed: September 30, 2021
    Publication date: April 28, 2022
    Inventors: Damon Woodard, Mark M. Tehranipoor, Navid Asadi-Zanjani, Ronald Wilson, Hangwei Lu, Nidish Vashistha
  • Patent number: 11308605
    Abstract: There is a need for more effective and efficient printed circuit board (PCB) design. This need can be addressed by, for example, solutions for performing automated PCB component estimation. In one example, a method includes identifying a PCB image of a PCB; performing chromaticity-based background subtraction on the PCB image to generate a background-subtracted PCB image; performing morphological noise removal on the background-subtracted PCB image to generate a noise-removed PCB image; and performing object localization on the noise-removed PCB image to identify one or more PCB component estimations within the noise-removed PCB image.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: April 19, 2022
    Assignee: University of Florida Research Foundation, Incorporated
    Inventors: Navid Asadi-Zanjani, Mark M. Tehranipoor, Mukhil Azhagan Mallaiyan Sathiaseelan
  • Patent number: 11270002
    Abstract: Disclosed are various embodiments for detecting hardware Trojans through information flow security verification. A file comprising register transfer level (HDL) code for an intellectual property core is loaded from memory. An asset within the intellectual property core is identified. An integrity verification or confidentiality verification of the HDL code that represents the asset is performed. An integrity violation or confidentiality violation within the HDL code as a result of performance of the integrity verification or confidentiality violation on the HDL code that represents the asset is detected. A malicious control point or a malicious observation point linked to the asset is identified. Finally, a trigger circuit for a hardware Trojan is identified in response to identification of the malicious control point or malicious observation point.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: March 8, 2022
    Assignee: University Of Florida Research Foundation, Inc.
    Inventors: Mark M. Tehranipoor, Adib Nahiyan, Domenic J. Forte
  • Patent number: 11222098
    Abstract: A dynamically obfuscated scan chain (DOSC) includes a control module designed to control memory loading, a linear feedback shift register (LFSR), a dynamic Obfuscation Key generator configured to use LFSR to generate a ?-bit protected Obfuscation Key, in order to confuse and change the test data into an output scan vectors when the Obfuscation Key update is triggered. The DOSC also includes a shadow chain, configured to input the ?-bit protected Obfuscation Key generated by the LFSR, and output k??×??-bit protected Obfuscation Keys, and obfuscated scan chains. The DOSC operating method includes: loading control vectors to LFSR from control module during initialization; generating the Obfuscation Key at an output of the LFSR; generating the Obfuscation Key bit by bit based at least in part on the shadow chain and the Obfuscation Key during a first scan clock after reset in order to confuse test patterns.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: January 11, 2022
    Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INCORPORATED
    Inventors: Mark M. Tehranipoor, Domenic J. Forte, Farimah Farahmandi, Adib Nahiyan, Fahim Rahman, Mohammad Sazadur Rahman
  • Publication number: 20210286905
    Abstract: A method includes in part, generating an electro-optical frequency map (EOFM) of an active layer of an integrated circuit (IC), retrieving a reference map of the IC, comparing the EOFM of the IC with the reference map to determine whether there is a match between an intensity of an identified region in the EOFM map and an intensity of a corresponding region of the reference map, and detecting one or more hardware trojans in the IC if there is no match. The reference map may be associated with a layout of an IC known not to include hardware trojans. The reference map also may be a second EOFM associated with the IC. Alternatively, the reference map may be generated by applying power to the IC, and applying a clock signal to the IC.
    Type: Application
    Filed: March 9, 2021
    Publication date: September 16, 2021
    Inventors: Mark M. Tehranipoor, Andrew Stern, Shahin Tajik, Farimah Farahmandi
  • Publication number: 20210264082
    Abstract: Embodiments of the present disclosure provide methods, apparatus, systems, computing devices, computing entities for setting deprocessing parameters used in conducting hardware deprocessing on a hardware.
    Type: Application
    Filed: February 4, 2021
    Publication date: August 26, 2021
    Inventors: Mark M. Tehranipoor, Navid Asadi-Zanjani, Olivia Pauline Paradis, Nitin Varshney
  • Publication number: 20210256188
    Abstract: There is a need for more effective and efficient printed circuit board (PCB) design. This need can be addressed by, for example, solutions for performing automated PCB component estimation. In one example, a method includes identifying a plurality of initial component estimations for the PCB; performing a shadow detection segmentation using the plurality of initial component estimations, a non-direct-lighting image, and one or more direct-lighting images to generate a first set of detected PCB components; performing a super-pixel segmentation using the plurality of initial component estimations and the non-direct-lighting-image to generate a second set of detected PCB components; and generating a bill of materials for the PCB based at least in part on the first set of detected PCB components and the second set of detected PCB components.
    Type: Application
    Filed: February 5, 2021
    Publication date: August 19, 2021
    Inventors: Navid Asadi-Zanjani, Nathan Jessurun, Mark M. Tehranipoor, Olivia Pauline Paradis
  • Publication number: 20210256683
    Abstract: There is a need for more effective and efficient printed circuit board (PCB) design. This need can be addressed by, for example, solutions for performing automated PCB component estimation. In one example, a method includes identifying a PCB image of a PCB; performing chromaticity-based background subtraction on the PCB image to generate a background-subtracted PCB image; performing morphological noise removal on the background-subtracted PCB image to generate a noise-removed PCB image; and performing object localization on the noise-removed PCB image to identify one or more PCB component estimations within the noise-removed PCB image.
    Type: Application
    Filed: January 14, 2021
    Publication date: August 19, 2021
    Inventors: Navid Asadi-Zanjani, Mark M. Tehranipoor, Mukhil Azhagan Mallaiyan Sathiaseelan
  • Patent number: 11087058
    Abstract: Embodiments of systems and methods for an FIB-aware anti-probing physical design flow are described in the present disclosure. Such embodiments incorporate new and improved security-critical steps in a physical design flow, in which the design is constrained to provide coverage on asset nets through an internal shield.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: August 10, 2021
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Domenic J. Forte, Mark M. Tehranipoor, Qihang Shi, Huanyu Wang, Haoting Shen
  • Publication number: 20210224449
    Abstract: Embodiments of systems and methods for an FIB-aware anti-probing physical design flow are described in the present disclosure. Such embodiments incorporate new and improved security-critical steps in a physical design flow, in which the design is constrained to provide coverage on asset nets through an internal shield.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 22, 2021
    Inventors: DOMENIC J. FORTE, MARK M. TEHRANIPOOR, QIHANG SHI, HUANYU WANG, HAOTING SHEN