Abstract: Lumped-element based class-E Chireix combiners are disclosed that are equivalents of a quarter-wave transmission line combiner. The proposed class-E equivalent power amplifier circuits that are used can be derived from a parallel tuned class-E implementation. The proposed low-pass equivalents can behave similarly in terms of class-E performance, but absorb the 90 degree to transmission line.

Abstract: A power amplifier circuit uses an output transistor and a cascode transistor. First and second drive circuits apply gate control signals to the two transistors, which rise and fall in synchronism, and this is such that the voltage drop across the cascode transistor is reduced (compared to a constant gate voltage being applied to the output transistor).

Abstract: An amplifier circuit comprising a driver (204, 304) configured to provide a switched mode input signal, a switching mode power amplifier (206, 306) configured to receive the switched mode input signal and provide an output signal for an external load (210, 310); and a sensor (208, 308) configured to sense the impedance of the external load (210, 310) The driver is configured to set the duty cycle of the switched mode input signal in accordance with the sensed impedance of the external load (210, 310).

Abstract: The invention provides a transmitter comprising two (or more) phase locked loops controlling respective oscillators, and implementing different phase modulation. Multiple phases are derived from the respective oscillators, and an edge rotator forms an output signal from a combination of the phases. The oscillators can operate at different frequencies, neither of which is an integer multiple of the other, whereas the output signals of the multiplexers of the first and second phase locked loops are closer in frequency and can be the same. This reduces the problem of pulling, with a circuit that can be implemented with low power and area and with the versatility of being digitally intensive.

Abstract: Power reduction in transmitters is very important. One method to realize reduction is to make use of switching power amplifiers (PA) that have a better efficiency. Switching PA concepts are only possible in combination with suitable modulation methods like pulse width modulation (PWM) and out-phasing concepts. However, PWM and out-phasing concepts rely on accurate phase control and duty cycle of the signals. Digitally generation of signals of variable duty cycles and phase is proposed without sacrificing their accuracy. Accordingly, a out-phasing power amplifier arrangement is disclosed, where the generation of the out-phasing angle (?) and duty cycles (d1 and d2) are controlled by a set of n-bit digital input words (D1, D2, D3, D4). The baseband phase information (?(t)) is phase modulated back to radio frequency and used as the clock signal of digital circuitry for phase and duty cycle generation after being frequency multiplied by 2n-1.

Abstract: A transmitter (200) comprises a first Chireix compensation circuit (230, 232, 238, 240) and a second Chireix compensation circuit (234, 236, 238, 240), wherein each Chireix compensation circuit has two inputs and two outputs. Two constant envelope input signals (22, 224) to be amplified are guided by a switch (226) to either the first or second Chireix amplifier unit. The selection as such depends on the phase (212) of the input signals to be amplified. The outputs of the two Chireix compensation circuits are cross-coupled to an inductive load (242). A Chireix inductor (238) and a Chireix capacitor (240), each having one terminal grounded, are also connected to the inductive load (242). By switching the signals to be amplified in response to their phase, optimum matching is ensured.

Abstract: A power amplifier, for example a class-E switching power amplifier, and corresponding method, comprising: a plurality of power transistors (16), for example twelve power transistors, providing a partitioned power transistor; and a voltage sensing module (22), comprising for example voltage dividers and inverters, digitally sensing the drain voltage (2) of the partitioned power transistor to control the number of power transistors of the plurality of power transistors (16) that are switched on or off thereby controlling the drain voltage (2) which is varying for example due to antenna mismatch. The power amplifier may further comprise a memory (24) coupled to the voltage sensing module (22) for storing a history of the drain voltage (2), e.g. a history of antenna mismatch.

Abstract: A pre-driver for an amplifier comprising a load network in which the following elements are connected in the following order: a resistor-an inductor-a capacitor. Also described are a power amplifier comprising such a pre-driver, a method of fabricating a pre-driver for an amplifier, and a method of performing power amplification.

Abstract: Method for setup of parameter values in a RF power amplifier circuit arrangement (200), wherein the amplifier circuit arrangement (200) comprises a first (210) and a second (220) amplification branch and is operated in an out-phasing configuration for amplification of RF input signals with modulated amplitude and modulated phase and respective circuit arrangements are disclosed. According to a first aspect a re-optimization of the dead-time or conversely the duty-cycle, respectively, the phase of the output signal after the combiner can be kept linear with respect to the out-phasing angle. Further, according to a second aspect, additionally to introduction of an optimally chosen dead-time, a non-coherent combiner (Lx, Lx*) can reduce crowbar current and switching losses due the output capacitance (Cds). Furthermore, according to a third aspect the reactive compensation can, additionally or alternatively, be controlled by operating both amplification branches at different duty-cycles.

Abstract: Various embodiments relate to a reconfigurable integrated digital Chireix out-phasing power amplifier for use in high power base stations is described and a related method of said design. The power amplifier may include a power transistor circuitry having plurality of power transistors and shunt-series circuitry (L1C1, L2C2), a broadband combiner having Chireix compensation elements, and an impedance matching filter. The power transistor circuitry, the broadband combiner, and the impedance matching filter are integrated in a unified package. In one embodiment, the power amplifier is implemented in a real switch-mode to facilitate integration of the Chireix compensation elements so as to make the Chireix power amplifier tunable. A method of driving Chireix power amplifier structure is also described.

Abstract: A bond wire transformer comprises a plurality of primary bond wires coupled in parallel; and a plurality of secondary bond wires coupled in parallel, each secondary bond wire being spaced apart from and oriented relative to a corresponding primary bond wire so as to achieve a desired mutual inductance between the corresponding primary and secondary bond wires, thereby providing magnetic coupling between the primary and secondary bond wires.

Abstract: A transmitter (200) comprises a first Chireix compensation circuit (230, 232, 238, 240) and a second Chireix compensation circuit (234, 236, 238, 240), wherein each Chireix compensation circuit has two inputs and two outputs. Two constant envelope input signals (22, 224) to be amplified are guided by a switch (226) to either the first or second Chireix amplifier unit. The selection as such depends on the phase (212) of the input signals to be amplified. The outputs of the two Chireix compensation circuits are cross-coupled to an inductive load (242). A Chireix inductor (238) and a Chireix capacitor (240), each having one terminal grounded, are also connected to the inductive load (242). By switching the signals to be amplified in response to their phase, optimum matching is ensured.

Abstract: Various embodiments relate to a reconfigurable integrated digital Chireix out-phasing power amplifier for use in high power base stations is described and a related method of said design. The power amplifier may include a power transistor circuitry having plurality of power transistors and shunt-series circuitry (L1C1, L2C2), a broadband combiner having Chireix compensation elements, and an impedance matching filter. The power transistor circuitry, the broadband combiner, and the impedance matching filter are integrated in a unified package. In one embodiment, the power amplifier is implemented in a real switch-mode to facilitate integration of the Chireix compensation elements so as to make the Chireix power amplifier tunable. A method of driving Chireix power amplifier structure is also described.

Abstract: A pre-driver for an amplifier comprising a load network in which the following elements are connected in the following order: a resistor-an inductor-a capacitor. Also described are a power amplifier comprising such a pre-driver, a method of fabricating a pre-driver for an amplifier, and a method of performing power amplification.

Abstract: A power amplifier, for example a class-E switching power amplifier, and corresponding method, comprising: a plurality of power transistors (16), for example twelve power transistors, providing a partitioned power transistor; and a voltage sensing module (22), comprising for example voltage dividers and inverters, digitally sensing the drain voltage (2) of the partitioned power transistor to control the number of power transistors of the plurality of power transistors (16) that are switched on or off thereby controlling the drain voltage (2) which is varying for example due to antenna mismatch. The power amplifier may further comprise a memory (24) coupled to the voltage sensing module (22) for storing a history of the drain voltage (2), e.g. a history of antenna mismatch.

Abstract: Power reduction in transmitters is very important. One method to realize reduction is to make use of switching power amplifiers (PA) that have a better efficiency. Switching PA concepts are only possible in combination with suitable modulation methods like pulse width modulation (PWM) and out-phasing concepts. However, PWM and out-phasing concepts rely on accurate phase control and duty cycle of the signals. Digitally generation of signals of variable duty cycles and phase is proposed without sacrificing their accuracy. Accordingly, a out-phasing power amplifier arrangement is disclosed, where the generation of the out-phasing angle (?) and duty cycles (d1 and d2) are controlled by a set of n-bit digital input words (D1, D2, D3, D4). The baseband phase information (?(t)) is phase modulated back to radio frequency and used as the clock signal of digital circuitry for phase and duty cycle generation after being frequency multiplied by 2n?1.

Abstract: Method for setup of parameter values in a RF power amplifier circuit arrangement (200), wherein the amplifier circuit arrangement (200) comprises a first (210) and a second (220) amplification branch and is operated in an out-phasing configuration for amplification of RF input signals with modulated amplitude and modulated phase and respective circuit arrangements are disclosed. According to a first aspect a re-optimization of the dead-time or conversely the duty-cycle, respectively, the phase of the output signal after the combiner can be kept linear with respect to the out-phasing angle. Further, according to a second aspect, additionally to introduction of an optimally chosen dead-time, a non-coherent combiner (Lx, Lx*) can reduce crowbar current and switching losses due the output capacitance (Cds). Furthermore, according to a third aspect the reactive compensation can, additionally or alternatively, be controlled by operating both amplification branches at different duty-cycles.