Patents by Inventor Mark Schmisseur

Mark Schmisseur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10390114
    Abstract: Examples may include sleds for a rack in a data center including physical accelerator resources and memory for the accelerator resources. The memory can be shared between the accelerator resources. One or more memory controllers can be provided to couple the accelerator resources to the memory to provide memory access to all the accelerator resources. Each accelerator resource can include a memory controller to access a portion of the memory while the accelerator resources can be coupled via an out-of-band channel to provide memory access to the other portions of the memory.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 20, 2019
    Assignee: INTEL CORPORATION
    Inventor: Mark A. Schmisseur
  • Publication number: 20190251034
    Abstract: A semiconductor chip is described. The semiconductor chip includes memory address decoder logic circuitry comprising different memory address bit manipulation paths to respectively impose different memory interleaving schemes for memory accesses directed to artificial intelligence information in a memory and non artificial intelligence information in the memory. The artificial intelligence information is to be processed with artificial intelligence logic circuitry disposed locally to the memory.
    Type: Application
    Filed: April 26, 2019
    Publication date: August 15, 2019
    Inventors: Francesc GUIM BERNAT, Dimitrios ZIAKAS, Mark A. SCHMISSEUR, Kshitij A. DOSHI, Kimberly A. MALONE
  • Patent number: 10372362
    Abstract: The present disclosure relates to a dynamically composable computing system comprising a computing fabric with a plurality of different disaggregated computing hardware resources having respective hardware characteristics. A resource manager has access to the respective hardware characteristics of the different disaggregated computing hardware resources and is configured to assemble a composite computing node by selecting one or more disaggregated computing hardware resources with respective hardware characteristics meeting requirements of an application to be executed on the composite computing node. An orchestrator is configured to schedule the application using the assembled composite computing node.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, John Chun Kwok Leung, Mark Schmisseur, Thomas Willhalm
  • Publication number: 20190235773
    Abstract: Examples relate to a memory controller or memory controller device for a memory pool of a computer system, to a management apparatus or management device for the computer system, and to an apparatus or device for a compute node of the computer system, and to corresponding methods and computer programs. The memory pool comprises computer memory that is accessible to a plurality of compute nodes of the computer system via the memory controller. The memory controller comprises interface circuitry for communicating with the plurality of compute nodes. The memory controller comprises control circuitry being configured to obtain an access control instruction via the interface circuitry. The access control instruction indicates that access to a portion of the computer memory of the memory pool is to be granted to one or more processes being executed by the plurality of compute nodes of the computer system.
    Type: Application
    Filed: April 9, 2019
    Publication date: August 1, 2019
    Inventors: Mark Schmisseur, Thomas Willhalm, Francesc Guim Bernat, Karthik Kumar, Suraj Prabhakaran
  • Publication number: 20190227737
    Abstract: Examples relate to a method for a memory module, a method for a memory controller, a method for a processor, to a memory module controller device or apparatus, to a memory controller device or apparatus, to a processor device or apparatus, a memory module, a memory controller, a processor, a computer system and a computer program. The method for the memory module comprises obtaining one or more memory write instructions of a group memory write instruction. The group memory write instruction comprises a plurality of memory write instructions to be executed atomically. The one or more memory write instructions relate to one or more memory addresses associated with memory of the memory module. The method comprises executing the one or more memory write instructions using previously unallocated memory of the memory module. The method comprises obtaining a commit instruction for the group memory write instruction.
    Type: Application
    Filed: December 17, 2018
    Publication date: July 25, 2019
    Inventors: Ginger GILSDORF, Karthik KUMAR, Thomas WILLHALM, Mark SCHMISSEUR, Francesc GUIM BERNAT
  • Patent number: 10359940
    Abstract: Provided are a method, system, computer readable storage medium, and switch for configuring a switch to assign partitions in storage devices to compute nodes. A management controller configures the switch to dynamically allocate partitions of at least one of the storage devices to the compute nodes based on a workload at the compute node.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: July 23, 2019
    Assignee: Intel Corporation
    Inventors: Mark A. Schmisseur, Mohan J. Kumar, Balint Fleischer, Debendra Das Sharma, Raj Ramanujan
  • Publication number: 20190171575
    Abstract: Techniques and mechanisms for capturing an image of processor state at one node of multiple nodes of a multi-processor platform, where the processor state includes some version of data which the node retrieved from another node of the platform. In an embodiment, a disruption of power is detected when a processor of a first node has a cached version of data which was retrieved from a second node. In response to detection of the disruption, the data is saved to a system memory of the first node as part of an image of the processor's state. The image further comprises address information, corresponding to the data, which indicates a memory location at the second node. In another embodiment, processor state is restored during a boot-up of the node, wherein the state includes the captured version of data which was previously retrieved from the second node.
    Type: Application
    Filed: January 31, 2019
    Publication date: June 6, 2019
    Inventors: Wei CHEN, Eswaramoorthi NALLUSAMY, Larisa NOVAKOVSKY, Mark SCHMISSEUR, Eric RASMUSSEN, Stephen VAN DOREN, Yen-Cheng LIU
  • Patent number: 10296217
    Abstract: Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Blaise Fanning, Mark A. Schmisseur, Raymond S. Tetrick, Robert J. Royer, Jr., David B. Minturn, Shane Matthews
  • Publication number: 20190102315
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to receive a request from a core, the request associated with a memory operation to read or write data, and the request comprising a first address and an offset, the first address to identify a memory location of a memory. Embodiments include performing a first iteration of a memory indirection operation comprising reading the memory at the memory location to determine a second address based on the first address, and determining a memory resource based on the second address and the offset, the memory resource to perform the memory operation for the computing resource or perform a second iteration of the memory indirection operation.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Applicant: INTEL CORPORATION
    Inventors: FRANCESC GUIM BERNAT, KARTHIK KUMAR, MARK SCHMISSEUR, THOMAS WILLHALM
  • Publication number: 20190102147
    Abstract: Examples may include a data center in which memory sleds are provided with logic to filter data stored on the memory sled responsive to filtering requests from a compute sled. Memory sleds may include memory filtering logic arranged to receive filtering requests, filter data stored on the memory sled, and provide filtering results to the requesting entity. Additionally, a data center is provided in which fabric interconnect protocols in which sleds in the data center communicate is provided with filtering instructions such that compute sleds can request filtering on memory sleds.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Applicant: INTEL CORPORATION
    Inventors: Karthik Kumar, Francesc Guim Bernat, Thomas Willhalm, Mark A. Schmisseur
  • Publication number: 20190102403
    Abstract: Techniques and apparatus for providing access to data in a plurality of storage formats are described. In one embodiment, for example, an apparatus may include logic, at least a portion of comprised in hardware coupled to the at least one memory, to determine a first storage format of a database operation on a database having a second storage format, and perform a format conversion process responsive to the first storage format being different than the second storage format, the format conversion process to translate a virtual address of the database operation to a physical address, and determine a converted physical address comprising a memory address according to the first storage format. Other embodiments are described and claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Applicant: INTEL CORPORATION
    Inventors: Mark A. Schmisseur, Thomas Willhalm, Francesc Guim Bernat, Karthik Kumar
  • Publication number: 20190102090
    Abstract: A memory controller method and apparatus, which includes a modification of at least one of a first timing scheme or a second timing scheme based on information about one or more data requests to be included in at least one of a first queue scheduler or a second queue scheduler, the first timing scheme indicating when one or more requests in the first queue scheduler are to be issued to the first memory set via a first memory set interface and over a channel, the second timing scheme indicating when one or more requests in the second queue scheduler are to be issued to the second memory set via a second memory set interface and over the channel. Furthermore, an issuance of a request to at least one of the first memory set in accordance with the modified first timing scheme or the second memory set in accordance with the modified second timing scheme may be included.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Francesc GUIM BERNAT, Karthik KUMAR, Thomas WILLHALM, Mark SCHMISSEUR
  • Patent number: 10235526
    Abstract: Various embodiments are directed to a system for accessing a self-encrypting drive (SED) upon resuming from a sleep power mode (SPM) state. An SED may be authenticated within a system, for example, upon resuming from a sleep state, based on unwrapping the SED passphrase with a SPM resume passphrase stored in a standby power register to receive power during the SPM state.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: March 19, 2019
    Assignee: INTEL CORPORATION
    Inventors: Asher Altman, Mark Schmisseur
  • Publication number: 20190065231
    Abstract: Technologies for migrating virtual machines (VMs) includes a plurality of compute sleds and a memory sled each communicatively coupled to a resource manager server. The resource manager server is configured to identify a compute sled of a for a virtual machine instance, allocate a first set of resources of the identified compute sled for the VM instance, associate a region of memory in a memory pool of a memory sled with the compute sled, and create the VM instance on the compute sled. The resource manager server is further configured to migrate the VM instance to another compute sled, associate the region of memory in the memory pool with the other compute sled, and start-up the VM instance on the other compute sled. Other embodiments are described herein.
    Type: Application
    Filed: December 30, 2017
    Publication date: February 28, 2019
    Inventors: Mark A. Schmisseur, Mohan J. Kumar, Murugasamy K. Nachimuthu, Slawomir Putyrski, Dimitrios Ziakas
  • Publication number: 20190065112
    Abstract: Technologies for utilizing a split memory pool include a compute sled. The compute sled includes multiple processors communicatively coupled together through a processor communication link. Each processor is to communicate with a different memory sled through a respective memory network dedicated to the corresponding processor and memory sled. The compute sled includes a compute engine to generate a memory access request to access a memory address in far memory. The far memory includes memory located on one of the memory sleds. The compute engine is also to determine, as a function of the memory address and a map of memory address ranges to the memory sleds, the memory sled on which to access the far memory, and send the memory access request to the determined memory sled to access the far memory associated with the memory address.
    Type: Application
    Filed: December 30, 2017
    Publication date: February 28, 2019
    Inventors: Mark A. Schmisseur, Aaron Gorius
  • Publication number: 20190050261
    Abstract: Technology for a memory pool arbitration apparatus is described. The apparatus can include a memory pool controller (MPC) communicatively coupled between a shared memory pool of disaggregated memory devices and a plurality of compute resources. The MPC can receive a plurality of data requests from the plurality of compute resources. The MPC can assign each compute resource to one of a set of compute resource priorities. The MPC can send memory access commands to the shared memory pool to perform each data request prioritized according to the set of compute resource priorities. The apparatus can include a priority arbitration unit (PAU) communicatively coupled to the MPC. The PAU can arbitrate the plurality of data requests as a function of the corresponding compute resource priorities.
    Type: Application
    Filed: March 29, 2018
    Publication date: February 14, 2019
    Inventors: Mark A. Schmisseur, Francesc Guim Bernat, Andrew J. Herdrich, Karthik Kumar
  • Publication number: 20190042408
    Abstract: Technologies for interleaving memory that is accessible via a shared memory pool include a memory sled. The memory sled includes a memory pool of byte-addressable memory devices. The memory sled also includes a memory pool controller coupled to the memory pool. The memory pool controller receives a request to allocate memory addresses of the memory pool to a compute sled. The memory pool controller determines an interleaving configuration for the compute sled as a function of memory characteristics of the compute sled and configures the memory addresses according to the determined interleaving configuration.
    Type: Application
    Filed: January 11, 2018
    Publication date: February 7, 2019
    Inventors: Mark Schmisseur, Dimitrios Ziakas, Murugasamy K. Nachimuthu
  • Publication number: 20190042122
    Abstract: Technologies for efficiently managing the allocation of memory in a shared memory pool include a memory sled. The memory sled includes a memory pool of byte-addressable memory devices. The memory sled also includes a memory pool controller coupled to the memory pool. The memory pool controller receives a request to provision memory to a compute sled. Further, the memory pool controller maps, in response to the request, each of the memory devices of the memory pool to the compute sled. The memory pool controller additionally assigns access rights to the compute sled as a function of one or more memory characteristics of the compute sled. The memory characteristics are indicative of an amount of memory in the memory pool to be used by the compute sled and the access rights are indicative of access permissions to one or more memory address ranges associated with the one or more memory devices.
    Type: Application
    Filed: December 28, 2017
    Publication date: February 7, 2019
    Inventors: Mark Schmisseur, Dimitrios Ziakas, Murugasamy K. Nachimuthu
  • Publication number: 20190045005
    Abstract: A method for replicating data to one or more distributed network nodes of a network is proposed. A movement of a moving entity having associated data stored on a first node of the network is estimated. The moving entity is physically moving between nodes of the network. According to the method, at least a second node of the network depending on the estimated movement is chosen. The method contains replicating the associated data of the first node to the second node or a group of nodes and contains managing how data is stored at those nodes based on the moving entity.
    Type: Application
    Filed: April 12, 2018
    Publication date: February 7, 2019
    Inventors: Timothy Verrall, Mark Schmisseur, Thomas Willhalm, Francesc Guim Bernat, Karthik Kumar
  • Publication number: 20190042488
    Abstract: Technology for a memory controller is described. The memory controller can receive a request from a data consumer node in a data center for training data. The training data indicated in the request can correspond to a model identifier (ID) of a model that runs on the data consumer node. The memory controller can identify a data provider node in the data center that stores the training data that is requested by the data consumer node. The data provider node can be identified using a tracking table that is maintained at the memory controller. The memory controller can send an instruction to the data provider node that instructs the data provider node to send the training data to the data consumer node to enable training of the model that runs on the data consumer node.
    Type: Application
    Filed: December 28, 2017
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: FRANCESC GUIM BERNAT, MARK A. SCHMISSEUR, KARTHIK KUMAR, THOMAS WILLHALM