Abstract: A receiver (50) for providing chip-to-chip communication in a superconductor integrated circuit. The receiver (50) includes a detector circuit (52) for asynchronously receiving an input current, a splitter circuit (60) connected to the detector circuit (52) for generating first and second signals, a delay circuit (62) receiving the second signal from the splitter circuit for generating a delayed signal and a register circuit (64) receiving the first signal from the splitter circuit (60) and the delayed signal from the delay circuit (62) for producing a single flux quantum (SFQ) pulse. The receiver (50) according to the present invention provides an asynchronous chip-to-chip communication between a multi-chip superconductive circuit having low input current without an external rf clock.

Abstract: In the context of a bus-mastering system, a device selector selects the device to control the bus by assigning “combined” priority values to the devices and selecting the device with the highest combined-priority value. The combined-priority values include relatively high-significance device-specific values and relatively low-significance arbitrary-rank values. At any given time, no two devices share the same arbitrary-rank values, and thus cannot share combined-priority values. Thus, there are no unresolved selections due to equal priorities. In accordance with the present invention, the arbitrary-rank values are varied in a round-robin fashion to minimize the bias inherent in conventional schemes using a priority encoder. This makes the device selection process conform better to the device-specific values, which are presumable selected to optimize system performance.

Abstract: A superconducting A/D converter (10) has an error correction system (70) for eliminating non-linearities in a primary quantizer (30). The converter (10) includes a primary quantizer (30), a primary SFQ counter (50), and the error correction system (70). The primary quantizer (30) generates primary SFQ pulses based on an average voltage of an analog input signal. The primary SFQ counter (50) converts the primary SFQ pulses into a digital output signal based on a frequency of the primary SFQ pulses. The error correction system (70) corrects the digital output signal based on the analog input signal and the primary SFQ pulses. Using the primary SFQ pulses to correct the digital output signal allows the converter (10) to take into account the non-linearities of the primary quantizer (30).

Abstract: An oscillator/multiply-accumulator AID converter (100) which simultaneously provides frequency downconversion, band pass filtering and analog-to-digital conversion of an analog signal, where the analog signal includes a carrier wave modulated with information by any known modulation technique. The converter (100) uses a superconducting, Josephson single flux quantum circuit operating as a voltage controlled oscillator (102). The voltage controlled oscillator (102) receives the analog signal to be converted, and generates a series of sharp, high frequency pulses based on the characteristics of the carrier signal. The series of pulses are applied to a gate circuit (104) that either passes or blocks the pulses depending on a gate control signal (103). When the pulses are passed by the gate circuit (104), a multiply-accumulator (106) multiplies the pulse by a binary coefficient (109) and accumulates the products (111) resulting from the multiplication during a predetermined time period.

Abstract: A set-associative cache-management method combines one-cycle reads and two-cycle pipelined writes. The one-cycle reads involve accessing data from multiple sets in parallel before a tag match is determined. Once a tag match is determined, it is used to select the one of the accessed cache memory locations to be coupled to the processor for the read operation. The two-cycle write involves finding a match in a first cycle and performing the write in the second cycle. During the write, the first stage of the write pipeline is available to begin another write operation. Also, the first-stage of the pipeline can be used to begin a two-cycle read operation-which results in a power saving relative to the one-cycle read operation. Due to the pipeline, there is no time penalty involved in the two-cycle read performed after the pipelined write. Also, instead of a wait, a no-op can be executed in the first stage of the write pipeline while the second stage of the pipeline is fulfilling a write request.

Abstract: A set-associative cache-management method utilizes both parallel reads and single-cycle single-set reads. The parallel reads involve accessing data from all cache sets in parallel before a tag match is determined. Once a tag match is determined, it is used to select the one of the accessed cache memory locations to be coupled to the processor for the read operation. Single-cycle single-set reads occur when the line address of one read operation matches the line address of an immediately preceding read operation satisfied from the cache. In such a case, only the set from which the previous read request was satisfied is accessed in the present read operation. The single-set reads save power relative to the parallel reads, while maintaining the speed advantages of the parallel reads over serial “tag-then-data” reads.

Abstract: A battery charging method (300) determines a current at which to start charging the battery which provides the capability for faster higher current sourcing capability. A start current(Istart)is determined based on the battery's cut off voltage, steady state voltage, and characteristic impedance (314). This start current is then compared and adjusted based on the rated power supply current for the power supply (316, 318) and rated charge current for the battery (320, 322). The adjusted current is then applied to the battery (324) at the beginning of the charge sequence to provide faster higher current sourcing capability.

Abstract: A set-associative cache-management method utilizes both parallel reads and single-cycle single-set reads. The parallel reads involve accessing data from all cache sets in parallel before a tag match is determined. Once a tag match is determined, it is used to select the one of the accessed cache memory locations to be coupled to the processor for the read operation. Single-cycle single-set reads occur when the line address of one read operation matches the line address of a immediately preceding read operation satisfied from the cache. In such a case, only the set from which the previous read request was satisfied is accessed in the present read operation. If a sequential read operation is indicated, the same-set can also be accessed to the exclusion of the other sets provided the requested address does not correspond to the beginning of a line address. (In that case, the sequential read crosses a cache-line boundary.

Abstract: A set-associative cache-management method combines one-cycle reads and two-cycle pipelined writes. The one-cycle reads involve accessing data from multiple sets in parallel before a tag match is determined. Once a tag match is determined, it is used to select the one of the accessed cache memory locations to be coupled to the processor for the read operation. The two-cycle write involves finding a match in a first cycle and performing the write in the second cycle. During the write, the first stage of the write pipeline is available to begin another write operation. Also, the first-stage of the pipeline can be used to begin a two-cycle read operation—which results in a power saving relative to the one-cycle read operation. Due to the pipeline, there is no time penalty involved in the two-cycle read performed after the pipelined write. Also, instead of a wait, a no-op can be executed in the first stage of the write pipeline while the second stage of the pipeline is fulfilling a write request.

Abstract: A set-associative cache-management method utilizes both parallel reads and single-cycle single-set reads. The parallel reads involve accessing data from all cache sets in parallel before a tag match is determined. Once a tag match is determined, it is used to select the one of the accessed cache memory locations to be coupled to the processor for the read operation. Single-cycle single-set reads occur when the line address of one read operation matches the line address of a immediately preceding read operation satisfied from the cache. In such a case, only the set from which the previous read request was satisfied is accessed in the present read operation. If a sequential read operation is indicated, the same-set can also be accessed to the exclusion of the other sets provided the requested address does not correspond to the beginning of a line address. (In that case, the sequential read crosses a cache-line boundary.

Abstract: A system for monitoring guiding and controlling an unmanned, unteathered flight vehicle, generally assumed to be moving through the earth's atmosphere at a high rate of speed. The system is comprised of on-board positional receiver and processing means coupled to a transceiver capable of combining such positional information with additional data relative to the health and status of the flight vehicle and transmitting the same to a ground station of compatible and simplified design. A preferred positional determination means is to utilize a form for GPS signal thereby affording one the opportunity to include appropriate processing software or additional componentry if necessary for base station purposes and thereby provide a relatively inexpensive system having a low probability of detection for intercept that simultaneously yields vastly improved operating performance characteristics over the mere translation of received GPS signals to down-link or to remote stations as known in the prior art.

Abstract: A system for monitoring guiding and controlling an unmanned, unteathered flight vehicle, generally assumed to be moving through the atmosphere of the earth at a high rate of speed. The system comprised an on-board positional receiver and processing means coupled to a transceiver capable of combining such positional information with additional data relative to the health and status of the flight vehicle and transmitting the same to a ground station of compatible and simplified design. A preferred positional determination means is to utilize a form for GPS signal thereby affording one the opportunity to include appropriate processing software or additional componentry if necessary for base station purposes and thereby provide a relatively inexpensive system having a low probability of detection for intercept that simultaneously yields vastly improved operating performance characteristics over the mere translation of received GPS signals to down-link or to remote stations as known in the prior art.

Abstract: An enhanced precision forward observation system and method employs a satellite positioning system receiver, range finder, and a compass/inclinometer. The satellite positioning system receiver is used to calculate an observer's position and target position estimation software employs data from multiple measurements for improved target position estimation.

Abstract: A global positioning system (GPS) receiver and high accuracy low power time source (HAL) are disclosed. The HAL provides a time source having an accuracy which is high enough for the receiver to achieve fast direct Y-code acquisition. The HAL includes an oscillator adapted to provide an uncompensated frequency signal at a desired frequency. Frequency conversion circuitry receives the uncompensated frequency signal and a control signal as inputs, and provides as an output a compensated frequency signal having an average compensated frequency which is closer to the desired frequency than is the average uncompensated frequency. A temperature sensor provides an output indicative of a temperature of the oscillator. Frequency error determining circuitry determines an error value, as a function of the temperature sensor output, which is indicative of a quantity of frequency error over time in the uncompensated frequency signal.

Abstract: This invention relates to pigment compositions prepared by precipitating a blend of (a) about 60 to about 95 percent by weight of a perylene pigment having the formula ##STR1## wherein R.sup.1 and R.sup.2 are independently C.sub.1 -C.sub.6 alkyl, C.sub.5 -C.sub.7 cycloalkyl, C.sub.7 -C.sub.16 aralkyl, or C.sub.6 -C.sub.10 aryl; and (b) about 5 to about 40 percent by weight of a polycyclic aromatic compound containg at least 5 aromatic rings wherein at least one ring is substituted with at least one keto group.

Abstract: This invention relates to a process for surface treating organic pigments by applying to the surface of an organic pigment(a) about 0.5 to about 15 percent by weight, relative to the pigment, of a phosphoric acid monoester having the formula ##STR1## wherein R is an optionally substituted saturated or unsaturated C.sub.5 -C.sub.40 aliphatic group, and M is hydrogen, metal, or ammonium;optionally in admixture with(b) 0 to about 10 percent by weight, relative to the phosphoric acid monoester, of a process additive.

Abstract: The present invention provides a filter sealing device for a filter element. The filter element includes an end portion defining an opening. The sealing device includes a body having a first section attached to a second section. The first section is positionable within the opening in the filter element with the second section facing an open end portion of the filter element. The first section has a larger coefficient of thermal expansion than the end portion of the filter element so that an increase in temperature results in the first section of the body expanding at a greater rate than the end portion of the filter element. These differing rates of expansion cause a compressive force to be exerted between the first section of the body and the end portion of the filter element.

Abstract: A filter assembly includes a housing having an inlet and an outlet, at least two filter elements stacked inside the housing, and a spacer positioned between the filter elements. The spacer includes a body having an opening which is larger than the inner diameter of at least one of the filter elements and is no smaller than about one-third of the outer diameter of a filter element. The spacer is free of any structure which extends into the opening.

Abstract: A pigment paste suitable for use in cationic electrodeposition is disclosed. The pigment paste comprises a cationic resinous grinding vehicle derived from an epoxy resin containing both quaternary ammonium and ternary sulfonium salt groups. Also disclosed are cationic electrodeposition paints containing the pigment paste and the use of these paints in the process of cationic electrodeposition. The paste improves the stability of lead-containing cationic electrodeposition paints.

Abstract: A cationic resin suitable for use as a pigment grinding vehicle is disclosed. The cationic resin is derived from an epoxy resin and contains ternary sulfonium groups and alkyl phenoxide groups. Pigment pastes derived from this cationic resin can be used in a method of cationic electrodeposition where they provide for films with high build and good appearance.