Abstract: A differential receiver with reduced common mode induced propagation delay variance. One implementation of a differential receiver includes a first differential amplifier, a second differential amplifier, and a first current source. The first differential amplifier includes a first transistor pair. The second differential amplifier includes a second transistor pair. The first current source is coupled to a drain node of a first transistor of the first transistor pair. The first current source is configured to generate a variable first current at the drain node as of function of a sum of a variable tail current of the first differential amplifier and a variable tail current of the second differential amplifier.

Abstract: An apparatus for equalizing channels is provided, which is generally transparent to link training. The apparatus generally includes equalization paths formed by an input circuit, a crossbar, and an output circuit and a controller. Each equalization path is coupled to at least one of the channels, and a controller has a VGA loop, a crossbar loop, and a driver loop. The AGC loop receives a first reference voltage and provides a gain control signal to the input circuit, and the gain control network comprises a replica of at least one of the equalization paths. The crossbar loop receives a second reference voltage and provides a crossbar control signal to the crossbar. The driver loop receives a third reference voltage and provides a driver control signal for the output circuit.

Abstract: An apparatus for equalizing channels is provided, which is generally transparent to link training. The apparatus generally includes equalization paths formed by an input circuit, a crossbar, and an output circuit and a controller. Each equalization path is coupled to at least one of the channels, and a controller has a VGA loop, a crossbar loop, and a driver loop. The AGC loop receives a first reference voltage and provides a gain control signal to the input circuit, and the gain control network comprises a replica of at least one of the equalization paths. The crossbar loop receives a second reference voltage and provides a crossbar control signal to the crossbar. The driver loop receives a third reference voltage and provides a driver control signal for the output circuit.

Abstract: Quadrature clocking schemes are widely used in modern communications systems, but often suffer from phase imbalance. Conventional solutions that attempt to address this phase imbalance, however, are generally large and use a substantial amount of power. Here, however, a correction circuit is provided that can locally correct for phase imbalance without the need for bulky and high power consuming circuitry.

Abstract: An apparatus is provided. The apparatus generally comprises a plurality of pairs of differential transmission lines. The plurality of pairs of differential transmission lines includes a set of pairs of differential transmission lines with each pair of differential transmission lines from the set of pairs of differential transmission lines including at least one twist to alternate current direction. Also, the plurality of differential transmission lines are arranged such that alternating current directions substantially eliminate cross-talk across the plurality of pairs of differential transmission lines.

Abstract: Methods and apparatus to provide an equalizer for analog adaptive control are disclosed. An example equalizer described herein includes a high frequency amplifier to receive an input signal and to amplify a high frequency portion of the input signal, a low frequency amplifier to receive the input signal and to amplify a low frequency portion of the input signal, and a weight factor controller to control a gain of the high frequency amplifier and a gain of the low frequency amplifier.

Abstract: Quadrature clocking schemes are widely used in modern communications systems, but often suffer from phase imbalance. Conventional solutions that attempt to address this phase imbalance, however, are generally large and use a substantial amount of power. Here, however, a correction circuit is provided that can locally correct for phase imbalance without the need for bulky and high power consuming circuitry.

Abstract: In bipolar CMOS or BiCMOS process technologies, drivers (such as mixed mode or hybrid mode drivers) using both bipolar and CMOS transistors (i.e., field effect transistors or FETs) may have undesirable properties, such as reduced speed, ringing, latch-up, or lower electrostatic discharge (ESD) performance. Here, a mixed or hybrid mode driver is provided that employs a current steering circuit (instead of voltages driven differential pair(s) as is done with conventional drivers) to generate pull-down currents that precisely match the voltages in the pull-up portions of driver. It increases the speed and produces smaller output common-mode voltage fluctuation over conventional drivers. Thus, the driver provided here can be produced in BiCMOS process technologies without the undesirable effects of conventional drivers.

Abstract: In bipolar CMOS or BiCMOS process technologies, drivers (such as mixed mode or hybrid mode drivers) using both bipolar and CMOS transistors (i.e., field effect transistors or FETs) may have undesirable properties, such as reduced speed, ringing, latch-up, or lower electrostatic discharge (ESD) performance. Here, a mixed or hybrid mode driver is provided that employs a current steering circuit (instead of voltages driven differential pair(s) as is done with conventional drivers) to generate pull-down currents that precisely match the voltages in the pull-up portions of driver. It increases the speed and produces smaller output common-mode voltage fluctuation over conventional drivers. Thus, the driver provided here can be produced in BiCMOS process technologies without the undesirable effects of conventional drivers.

Abstract: Traditionally, complementary metal oxide semiconductor (CMOS) and bipolar transistors have been separately employed in low voltage differential signal (LVDS) drivers. Here, a hybridized LVDS driver is provided with an input stage that uses CMOS transistors and output stages that use bipolar transistors. As a result of this hybridization, the LVDS driver has superior functional characteristics compared to conventional LVDS drivers as well as being able to function with a supply range between about 1.8V and 3.3V.

Abstract: Traditionally, complementary metal oxide semiconductor (CMOS) and bipolar transistors have been separately employed in low voltage differential signal (LVDS) drivers. Here, a hybridized LVDS driver is provided with an input stage that uses CMOS transistors and output stages that use bipolar transistors. As a result of this hybridization, the LVDS driver has superior functional characteristics compared to conventional LVDS drivers as well as being able to function with a supply range between about 1.8V and 3.3V.

Abstract: For differential signal transmission (especially in high speed applications), intra-pair skew between paths carrying complementary portions of a differential signal can significantly affect performance. Conventional de-skew circuits employ simple filters (i.e., low-pass filters) to operate as delay elements to account for skew; however, these filters can distort the differential signal, which can also adverse affect performance. Here, an all-pass, adjustable delay element and de-skew circuit are provided to allow for compensation of skew without degrading the differential signal as conventional circuit do and, thus, having better performance characteristics.

Abstract: A self-calibrating, adaptive equalization system for generating an ideal digital signal is disclosed. The adaptive equalization system includes an equalizer and a high-gain buffer. The equalizer includes a first equalizer loop that feeds-back a control voltage to the equalizer and the high-gain buffer that includes a second equalizer loop that feeds-back a high-pass-to-low-pass filter ratio signal. Each of the first and second equalizer loops has a high-pass and a low-pass filter, rectifying circuits for each of the filters, and an integrating circuit that compares signal energy output from the rectifiers. The adaptive equalization system generates an ideal digital signal.

Abstract: In the many microelectronics applications, delays present in circuitry can affect both the design and the function of the circuitry. One example of delays impacting the function of a circuit is a relaxation oscillator, where delays present in comparator circuits and latches can cause its frequency to vary beyond desired ranges. Here, a relaxation circuit with delay compensation is described.

Abstract: A bidirectional repeater and data multiplexer for serial data has A-side 12C port devices A1-A4 coupled to comparators 302-308 and pull-downs to ground 316-322. Comparator outputs are coupled responsive to select lines S1-S4 of N:1 Select 310 to terminal A1 of bidirectional control 210 to control pull-down to non-zero low voltage Vp 206 at B-side device B. An inverting comparator 208 coupled to terminal B1 of bidirectional control 210 responds to input threshold voltage Vt less than low voltage Vp, to prevent data lockup due to data flowback to devices A1-A4. Output data from comparator 208 is coupled responsive to select lines S1-S4 of 1:N Select 312 to control pull-downs 316-322. This selectively repeats routing of device A1-A4 data to device B. Data from device B is selectively routed to pull-downs of devices A1-A4.

Abstract: In the many microelectronics applications, delays present in circuitry can affect both the design and the function of the circuitry. One example of delays impacting the function of a circuit is a relaxation oscillator, where delays present in comparator circuits and latches can cause its frequency to vary beyond desired ranges. Here, a relaxation circuit with delay compensation is described.

Abstract: An apparatus for regulating voltage for at least one differential transistor pair having a voltage follower buffer, the voltage follower section having a first voltage-temperature response, includes: (a) a differential amplifier having two input loci and an output locus, a first input locus of the two input loci receiving a reference voltage; (b) a temperature responsive unit coupled between the output locus and ground; and (c) a feedback line coupled between the temperature responsive unit and a second input locus of the two input loci. The temperature responsive unit has a second voltage-temperature response similar to the first voltage-temperature response.

Abstract: A self-calibrating, adaptive equalization system for generating an ideal digital signal is disclosed. The adaptive equalization system includes an equalizer and a high-gain buffer. The equalizer includes a first equalizer loop that feeds-back a control voltage to the equalizer and the high-gain buffer that includes a second equalizer loop that feeds-back a high-pass-to-low-pass filter ratio signal. Each of the first and second equalizer loops has a high-pass and a low-pass filter, rectifying circuits for each of the filters, and an integrating circuit that compares signal energy output from the rectifiers. The adaptive equalization system generates an ideal digital signal.

Abstract: A bidirectional repeater and data multiplexer for serial data has A-side 12C port devices A1-A4 coupled to comparators 302-308 and pull-downs to ground 316-322. Comparator outputs are coupled responsive to select lines S1-S4 of N:1 Select 310 to terminal A1 of bidirectional control 210 to control pull-down to non-zero low voltage Vp 206 at B-side device B. An inverting comparator 208 coupled to terminal B1 of bidirectional control 210 responds to input threshold voltage Vt less than low voltage Vp, to prevent data lockup due to data flowback to devices A1-A4. Output data from comparator 208 is coupled responsive to select lines S1-S4 of 1:N Select 312 to control pull-downs 316-322. This selectively repeats routing of device A1-A4 data to device B. Data from device B is selectively routed to pull-downs of devices A1-A4.

Abstract: A bidirectional repeater and data multiplexer for serial data has A-side I2C port devices A1-A4 coupled to comparators 302-308 and pulldowns to ground 316-322. Comparator outputs are coupled responsive to select lines S1-S4 of N:l Select 310 to terminal A1 of bidirectional control 210 to control pulldown to non-zero low voltage Vp 206 at B-side device B. An inverting comparator 208 coupled to terminal B1 of bidirectional control 210 responds to input threshold voltage Vt less than low voltage Vp, to prevent data lockup due to data flowback to devices A1-A4. Output data from comparator 208 is coupled responsive to select lines S1-S4 of 1:N Select 312 to control pulldowns 316-322. This selectively repeats routing of device A1-A4 data to device B. Data from device B is selectively routed to pulldowns of devices A1-A4.