Patents by Inventor Marko J Tadjer

Marko J Tadjer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9305858
    Abstract: An array of through-silicon vias (TSVs) are formed in a silicone substrate. The vias can be tapered such that the diameter of the via at the surface of the substrate is larger than the diameter of the via at its bottom, with the diameter varying continuously along its depth. After the via is formed, it is seeded with a thin layer of nanocrystalline diamond (NCD) particles, and a NCD film is grown on the bottom and along the sidewalls of the via. The presence of the diamond-filled vias provides improved thermal management to semiconductor devices formed on the silicon substrate.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: April 5, 2016
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Karl D. Hobart, Marko J. Tadjer, Tatyana I. Feygelson, Bradford B. Pate, Travis J. Anderson
  • Publication number: 20150362374
    Abstract: This disclosure describes a microbolometer sensor element and microbolometer array imaging devices optimized for infrared radiation detection that are enabled using atomic layer deposition (ALD) of vanadium oxide material layer (VOx) for a temperature sensitive resistor.
    Type: Application
    Filed: June 3, 2015
    Publication date: December 17, 2015
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Virginia D. Wheeler, Francis J. Kub, Charles R. Eddy, JR., Marko J. Tadjer
  • Publication number: 20150362763
    Abstract: A smart window comprising a transparent substrate, a transparent low emittance layer on the transparent substrate, a variable emittance material layer on the substrate or transparent low emittance layer, and a protection material layer on the variable emittance material layer.
    Type: Application
    Filed: June 4, 2015
    Publication date: December 17, 2015
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Virginia D. Wheeler, Francis J. Kub, Charles R. Eddy, JR., Marko J. Tadjer
  • Publication number: 20150348866
    Abstract: An array of through-silicon vias (TSVs) are formed in a silicone substrate. The vias can be tapered such that the diameter of the via at the surface of the substrate is larger than the diameter of the via at its bottom, with the diameter varying continuously along its depth. After the via is formed, it is seeded with a thin layer of nanocrystalline diamond (NCD) particles, and a NCD film is grown on the bottom and along the sidewalls of the via. The presence of the diamond-filled vias provides improved thermal management to semiconductor devices formed on the silicon substrate.
    Type: Application
    Filed: August 7, 2015
    Publication date: December 3, 2015
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Karl D. Hobart, Marko J. Tadjer, Tatyana I. Feygelson, Bradford B. Pate, Travis J. Anderson
  • Patent number: 9196703
    Abstract: A method for fabricating a semiconductor device, such as a GaN high electron mobility transistor (HEMT) device, including etching a thermal via into a back-side of a semiconductor substrate and depositing a diamond nucleation seed layer across the back-side of the substrate. The method further includes coating the diamond nucleation with a mask layer and removing mask material outside of the thermal via on the planar portions of the back-side of the substrate. The method includes removing portions of the diamond nucleation layer on the planar portions and then removing the remaining portion of the mask material in the thermal via. The method then includes depositing a bulk diamond layer within the thermal via on the remaining portion of the diamond nucleation layer so that diamond only grows in the thermal via and not on the planar portions of the substrate.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: November 24, 2015
    Assignees: Northrop Grumman Systems Corporation, The United States of America, as Represented by the Secretary of the Navy, The Regents of the University of California
    Inventors: Karl D. Hobart, Tatyana I. Feygelson, Eugene I. Imhoff, Travis J. Anderson, Joshua D. Caldwell, Andrew D. Koehler, Bradford B. Pate, Marko J. Tadjer, Rajinder S. Sandhu, Vincent Gambin, Gregory Lewis, Ioulia Smorchkova, Mark Goorsky, Jeff McKay
  • Patent number: 9159641
    Abstract: An array of through-silicon vias (TSVs) are formed in a silicone substrate. The vias can be tapered such that the diameter of the via at the surface of the substrate is larger than the diameter of the via at its bottom, with the diameter varying continuously along its depth. After the via is formed, it is seeded with a thin layer of nanocrystalline diamond (NCD) particles, and a NCD film is grown on the bottom and along the sidewalls of the via. The presence of the diamond-filled vias provides improved thermal management to semiconductor devices formed on the silicon substrate.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: October 13, 2015
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Karl D. Hobart, Marko J. Tadjer, Tatyana I. Feygelson, Bradford B. Pate, Travis J. Anderson
  • Publication number: 20150287613
    Abstract: A method for removing existing basal plane dislocations (BPDs) from silicon carbide epilayers by using a pulsed rapid thermal annealing process where the BPDs in the epilayers were eliminated while preserving the epitaxial surface. This high temperature, high pressure method uses silicon carbide epitaxial layers with a carbon cap to protect the surface. These capped epilayers are subjected to a plurality of rapid heating and cooling cycles.
    Type: Application
    Filed: April 6, 2015
    Publication date: October 8, 2015
    Inventors: Marko J. Tadjer, Boris N. Feigelson, Nadeemullah A. Mahadik, Robert E. Stahlbush, Eugene A. Imhoff, Jordan Greenlee
  • Patent number: 9129799
    Abstract: A method to remove basal plane dislocations in post growth silicon carbide epitaxial layers by capping post growth silicon carbide epilayers with a graphite cap and annealing the capped silicon carbon epilayers at a temperature of 1750° C. or greater with a nitrogen overpressure of 60-110 psi, wherein basal plane dislocations in the epilayers are removed while surface morphology is preserved. Also disclosed is the related silicon carbide substrate material made by this method.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: September 8, 2015
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Nadeemullah A. Mahadik, Robert E. Stahlbush, Marko J. Tadjer, Eugene A. Imhoff, Boris N. Feigelson
  • Publication number: 20150155166
    Abstract: A method to remove basal plane dislocations in post growth silicon carbide epitaxial layers by capping post growth silicon carbide epilayers with a graphite cap and annealing the capped silicon carbon epilayers at a temperature of 1750° C. or greater with a nitrogen overpressure of 60-110 psi, wherein basal plane dislocations in the epilayers are removed while surface morphology is preserved. Also disclosed is the related silicon carbide substrate material made by this method.
    Type: Application
    Filed: September 26, 2014
    Publication date: June 4, 2015
    Inventors: Nadeemullah A. Mahadik, Robert E. Stahlbush, Marko J. Tadjer, Eugene A. Imhoff, Boris N. Feigelson
  • Publication number: 20150060947
    Abstract: A field effect transistor having a diamond gate electrode and a process for forming the same. In some embodiments, the device is an AlGaN/GaN high-electron-mobility transistor (HEMT). The diamond gate electrode is formed so that it directly contacts the barrier layer. In some embodiments, the diamond gate electrode is formed from boron-doped nanocrystalline diamond (NCD), while in other embodiments, the diamond gate electrode is formed from single crystal diamond.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 5, 2015
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Andrew D. Koehler, Travis J. Anderson, Marko J. Tadjer, Tatyana I. Feygelson, Karl D. Hobart
  • Publication number: 20150056763
    Abstract: A method for fabricating a semiconductor device, such as a GaN high electron mobility transistor (HEMT) device, including etching a thermal via into a back-side of a semiconductor substrate and depositing a diamond nucleation seed layer across the back-side of the substrate. The method further includes coating the diamond nucleation with a mask layer and removing mask material outside of the thermal via on the planar portions of the back-side of the substrate. The method includes removing portions of the diamond nucleation layer on the planar portions and then removing the remaining portion of the mask material in the thermal via. The method then includes depositing a bulk diamond layer within the thermal via on the remaining portion of the diamond nucleation layer so that diamond only grows in the thermal via and not on the planar portions of the substrate.
    Type: Application
    Filed: August 20, 2014
    Publication date: February 26, 2015
    Inventors: Karl D. Hobart, Tatyana I. Feygelson, Eugene A. Imhoff, Travis J. Anderson, Joshua D. Caldwell, Andrew D. Koehler, Bradford B. Pate, Marko J. Tadjer, Randijer S. Sandhu, Vincent Gambin, Gregory Lewis, Ioulia Smorchkova, Mark Goorsky, Jeff McKay
  • Publication number: 20140264777
    Abstract: An array of through-silicon vias (TSVs) are formed in a silicone substrate. The vias can be tapered such that the diameter of the via at the surface of the substrate is larger than the diameter of the via at its bottom, with the diameter varying continuously along its depth. After the via is formed, it is seeded with a thin layer of nanocrystalline diamond (NCD) particles, and a NCD film is grown on the bottom and along the sidewalls of the via. The presence of the diamond-filled vias provides improved thermal management to semiconductor devices formed on the silicon substrate.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Karl D. Hobart, Marko J. Tadjer, Tatyana I. Feygelson, Bradford B. Pate, Travis J. Anderson
  • Patent number: 8445383
    Abstract: A heterojunction between thin films of NCD and 4H—SiC was developed. Undoped and B-doped NCDs were deposited on both n? and p? SiC epilayers. I-V measurements on p+ NCD/n? SiC indicated Schottky rectifying behavior with a turn-on voltage of around 0.2 V. The current increased over eight orders of magnitude with an ideality factor of 1.17 at 30° C. Ideal energy-band diagrams suggested a possible conduction mechanism for electron transport from the SiC conduction band to either the valence band or acceptor level of the NCD film.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: May 21, 2013
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Karl D. Hobart, Tatyana I Feygelson, Marko J Tadjer, Joshua D. Caldwell, Kendrick X Liu, Francis J. Kub, Michael A Mastro, James E Butler
  • Patent number: 7915143
    Abstract: A method of reversing Shockley stacking fault expansion includes providing a bipolar or a unipolar SiC device exhibiting forward voltage drift caused by Shockley stacking fault nucleation and expansion. The SiC device is heated to a temperature above 150° C. A current is passed via forward bias operation through the SiC device sufficient to induce at least a partial recovery of the forward bias drift.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: March 29, 2011
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Joshua D. Caldwell, Robert E Stahlbush, Karl D Hobart, Marko J Tadjer, Orest J Glembocki
  • Publication number: 20090273390
    Abstract: A method of reversing Shockley stacking fault expansion includes providing a bipolar or a unipolar SiC device exhibiting forward voltage drift caused by Shockley stacking fault nucleation and expansion. The SiC device is heated to a temperature above 150° C. A current is passed via forward bias operation through the SiC device sufficient to induce at least a partial recovery of the forward bias drift.
    Type: Application
    Filed: April 30, 2009
    Publication date: November 5, 2009
    Inventors: JOSHUA D. CALDWELL, Robert E. Stahlbush, Karl D. Hobart, Marko J. Tadjer, Orest J. Glembocki
  • Publication number: 20090090918
    Abstract: A heterojunction between thin films of NCD and 4H—SiC was developed. Undoped and B-doped NCDs were deposited on both n? and p? SiC epilayers. I-V measurements on p+ NCD/n? SiC indicated Schottky rectifying behavior with a turn-on voltage of around 0.2 V. The current increased over eight orders of magnitude with an ideality factor of 1.17 at 30° C. Ideal energy-band diagrams suggested a possible conduction mechanism for electron transport from the SiC conduction band to either the valence band or acceptor level of the NCD film.
    Type: Application
    Filed: September 5, 2008
    Publication date: April 9, 2009
    Inventors: Karl D. Hobart, Tatyana I. Feygelson, Marko J. Tadjer, Joshua D. Caldwell, Kendrick X. Liu, Francis J. Kub