Abstract: Structure and method for fabricating a system on chip with an on-chip RF shield including interconnect metallization is described. In one embodiment, the system on chip includes an RF circuitry disposed on a first portion of a top surface of a substrate, and a semiconductor circuitry disposed on a second portion of the top surface of the substrate. An interconnect RF barrier is disposed between the RF circuitry and the semiconductor circuitry, the interconnect RF barrier coupled to a ground potential node.

Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also includes an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. In the molding compound a contact via is arranged.

Abstract: Thin integrated semiconductor devices are produced by being embedded in a molding compound matrix in such a way that a composite is formed. The semiconductor devices are first embedded in the matrix and then thinned after being embedded. The thin integrated semiconductor devices are singulated by forming separating cuts into the molding compound matrix between adjacent devices.

Abstract: For the vertical electrical connection of a number of components, an electronic structure with at least two components has solderable connecting elements, which include at least one socket element and a solder ball stacked on the socket element. The socket element has a cylindrical core of an electrically conducting first material with a lateral surface, a bottom surface and a top surface. The core is surrounded with a cladding of an electrically insulating second material in such a way that the lateral surface of the core is covered by the cladding and the top surface and the bottom surface are kept free of the cladding.

Abstract: A semiconductor device includes a semiconductor chip and a metal layer electrically coupled to the semiconductor chip. The semiconductor device includes an array of solder balls coupled to the metal layer and a front side protect material directly contacting the metal layer and laterally surrounding a portion of at least a plurality of solder balls. The front side protect material is configured to become fluid during solder reflow.

Abstract: A semiconductor module. One embodiment provides at least two semiconductor chips placed on a carrier. The at least two semiconductor chips are then covered with a molding material to form a molded body. The molded body is thinned until the at least two semiconductor chips are exposed. Then, the carrier is removed from the at least two semiconductor chips. The at least two semiconductor chips are singulated.

Abstract: A semiconductor module includes: a plastic housing composition; at least one semiconductor chip with an active top side, a coplanar underside of the semiconductor module including the active top side of the semiconductor chip(s) and a surface of the plastic housing composition; a wiring structure arranged on the coplanar underside, the wiring structure including a center region and edge regions, with external contact areas distributed uniformly in the center region; external contacts arranged on the external contact areas of the wiring structure; and at least one surface-mountable semiconductor component arranged on the wiring structure in at least one of the edge regions, the surface-mountable semiconductor component(s) having a structural height that is less than the height of the external contacts.

Abstract: A carrier sheet with an adhesive film includes a heat-resistant base film with an upper side and an underside, and a thermoactive adhesive layer arranged on the underside of the base film and oriented toward the carrier sheet. The upper side of the base film includes an adhesive layer with semiconductor chips fixed on it, the semiconductor chips being surrounded by deactivated regions of the adhesive layer of the film upper side.

Abstract: A semiconductor device and method. One embodiment provides an encapsulation plate defining a first main surface and a second main surface opposite to the first main surface. The encapsulation plate includes multiple semiconductor chips. An electrically conductive layer is applied to the first and second main surface of the encapsulation plate at the same time.

Abstract: A semiconductor device is disclosed. One embodiment provides an arrangement of a plurality of semiconductor chips arranged side by side in a spaced apart relationship. A first material fills at least partly the spacings between adjacent semiconductor chips. A second material is arranged over the semiconductor chips and the first material. A coefficient of thermal expansion of the first material is selected to adapt the lateral thermal expansion of the arrangement in a plane intersecting the first material and the semiconductor chips to the lateral thermal expansion of the arrangement in a plane intersecting the second material.

Abstract: A method for fabricating a device, a semiconductor chip package, and a semiconductor chip assembly is disclosed. One embodiment includes applying at least one semiconductor chip on a first form element. At least one element is applied on a second form element. A material is applied on the at least one semiconductor chip and on the at least one element.

Abstract: Stacked semiconductor chips are disclosed. One embodiment provides a method including a first substrate having a first surface and an opposing second surface. The first substrate includes an array of first connection elements on the first surface of the first substrate. A second substrate has a first surface and an opposing second surface. The second substrate includes an array of second connection elements on the first surface of the second substrate. The first connection elements is attached to the second connection elements; and is thinning at least one of the first substrate and the second substrate after the attachment of the first connection elements to the second connection elements.

Abstract: An integrated circuit device includes a carrier defining a surface with a semiconductor chip including an integrated circuit attached to the carrier. An insulation layer is disposed over the carrier, extending above the surface of the carrier a first distance at a first location and a second distance at a second location. A transition area is defined between the first and second locations, wherein the transition area defines a non-right angle relative to the surface.

Abstract: An integrated circuit includes a substrate including a contact pad, a redistribution line coupled to the contact pad, and a dielectric material layer between the substrate and the redistribution line. The integrated circuit includes a solder ball coupled to the redistribution line and a parylene material layer sealing the dielectric material layer and the redistribution line.

Abstract: A semiconductor device is disclosed. One embodiment includes a semiconductor substrate and at least two insulating elements located above the semiconductor substrate or above a mold compound embedding the semiconductor substrate. The at least two insulating elements have a first face facing the semiconductor substrate or the mold compound and a second face facing away from the semiconductor substrate or the mold compound. A conductive element for each of the at least two insulating elements extends from the first face of the insulating element to the second face of the insulating element.

Abstract: A description is given of a device comprising a first semiconductor chip, a molding compound layer embedding the first semiconductor chip, a first electrically conductive layer applied to the molding compound layer, a through hole arranged in the molding compound layer, and a solder material filling the through hole.

Abstract: A semiconductor device and method is disclosed. In one embodiment, the method includes placing a first semiconductor over an electrically conductive carrier. The first semiconductor is covered with a molding compound. A through hole is formed in the molding compound. A first material is deposited in the through hole.

Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. In the molding compound a contact via is arranged.

Abstract: A method and apparatus for encapsulating items such as electronic devices. A mold material is dispensed onto the electronic device and the device is situated between first and second molds. One mold is moved towards the other so as to vary the size of a cavity defined by the first and second molds. A vacuum is applied to the cavity and the vacuum is varied in response to the size of the cavity. The vacuum can be varied in response to a predetermined vacuum profile. For example, in certain embodiments the vacuum is varied in response to the position of the first mold relative to the second mold, wherein the vacuum is increased as the cavity height is reduced.