Abstract: The techniques of this disclosure may digitally generate a driver signal with a period (or frequency) at a finer resolution than can be achieved by simply counting clock cycles of a system clock. The driver signal may be configured to trigger based on single output clock signal that may be phase-shifted relative to the master system clock. A clock phase shift circuit may increment the phase shift of the output clock signal to any fraction relative to the master system clock. A driver signal generated based on the phase-shifted output clock may achieve the high resolution in frequency desirable when controlling some pulse-width modulated circuits, such as an LLC converter.

Abstract: Techniques are disclosed for a level shifter configured to adjust current flow in response to measured current fluctuations due to common mode noise in the level shifter. For example, the level shifter includes a low-side control circuit configured to adjust a first current flowing into a first low-side terminal of an active high voltage level shifter device in response to a difference between the first low-side current and a second low-side current flowing into a second low-side terminal of an inactive high voltage level shifter device. The level shifter further includes a high-side receiver circuit configured to detect a difference between a first high-side current flowing into a first high-side terminal of the active high voltage level shifter device and a second high-side current flowing into a second high-side terminal of the inactive high voltage level shifter device.

Abstract: The techniques of this disclosure may digitally generate a driver signal with a period (or frequency) at a finer resolution than can be achieved by simply counting clock cycles of a system clock. The driver signal may be configured to trigger based on single output clock signal that may be phase-shifted relative to the master system clock. A clock phase shift circuit may increment the phase shift of the output clock signal to any fraction relative to the master system clock. A driver signal generated based on the phase-shifted output clock may achieve the high resolution in frequency desirable when controlling some pulse-width modulated circuits, such as an LLC converter.

Abstract: Semiconductor component comprising at least two semiconductor regions are disclosed. In one embodiment the semiconductor regions of the semiconductor component are electrically isolated from one another by an insulator, and a deposited, patterned, metallic layer extends over the semiconductor regions and over the insulator.

Abstract: A switching converter includes a transistor arrangement having a plurality of n transistors, with n?2, each including a gate terminal, and a load path between a source and a drain terminal, and at least m, with m?n and m?1 of the n transistors having a control terminal. The control terminal of each of the m transistors is configured to receive a control signal that adjusts an activation state of the transistor. The load paths of the plurality of n transistors are connected in parallel to form a load path of the transistor arrangement. A drive circuit is configured to adjust the activation state of the m transistors.

Abstract: Techniques are disclosed for a level shifter configured to adjust current flow in response to measured current fluctuations due to common mode noise in the level shifter. For example, the level shifter includes a low-side control circuit configured to adjust a first current flowing into a first low-side terminal of an active high voltage level shifter device in response to a difference between the first low-side current and a second low-side current flowing into a second low-side terminal of an inactive high voltage level shifter device. The level shifter further includes a high-side receiver circuit configured to detect a difference between a first high-side current flowing into a first high-side terminal of the active high voltage level shifter device and a second high-side current flowing into a second high-side terminal of the inactive high voltage level shifter device.

Abstract: A method for transmitting data in a direction of transmission of a clock signal, wherein positive and negative edges of the clock signal are transmitted by pulses with opposite polarity, wherein the polarity of the pulses is not inverted when no data is transmitted, and wherein the polarity of at least one pulse is inverted when data is transmitted.

Abstract: An electronic switch is connected in series with a load dependent on an input signal. The electronic switch is operated in a first operation mode for a first time period after a signal level of the input signal has changed from an off-level to an on-level. The first operation mode includes driving the electronic switch dependent on a voltage across the load and dependent on a temperature of the electronic switch. The electronic switch is operated in a second operation mode after the first time period. The second operation mode includes driving the electronic switch dependent on the temperature according to a hysteresis curve.

Abstract: A method for operating a power factor correction circuit is provided which may include the steps of providing a plurality of N switched-mode converter circuits each comprising an nth inductor, where N is at least 2, starting a switching pulse for the nth switched-mode converter circuit when the following conditions are fulfilled: the nth inductor of the nth switched-mode converter circuit has a predefined magnetization state; and a predefined time period has elapsed since the start of a switching pulse for an mth switched-mode converter circuit, where m=n?1 in case n>1 and m=N in case n=1. The predefined time period is a predefined fraction of the time period from the start of a previous switching pulse for the nth switched-mode converter circuit to a time when the nth inductor of the nth switched-mode converter circuit has the predefined magnetization state.

Abstract: Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

Abstract: System and method for adaptively altering a power supply's dead time. A method comprises detecting a start of a dead time, detecting an ending condition of the dead time, and ending the dead time. The detecting of the ending condition is based on a first current flowing through a lower portion of the power supply or a second current flowing through a gate driver of a lower switching element in the power supply.

Abstract: A embodiment relates to a current estimation circuitry for a converter comprising: an integrator for integrating a voltage across an inductor of the converter; a current sense unit for obtaining a signal that is associated with the current flowing through at least one of the electronic switches of the converter; and a control unit for adjusting at least two parameters of the integrator based on comparing the output of the integrator with the signal provided by the current sense unit.

Abstract: Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

Abstract: In various embodiments, a circuit is provided including a supply terminal, a logic circuit, an inverter and a control transistor which may include a body region, first and second source/drain regions, a gate insulating region having a layer thickness and a gate region. The first source/drain region may be coupled to the supply terminal. The logic circuit may have an internal supply terminal connected to the second source/drain region of the control transistor and a plurality of transistors each having a gate insulating region having a second layer thickness. The inverter input may be coupled to the internal supply terminal of the logic circuit and the output to the gate region of the control transistor. The inverter may include a transistor with a gate insulating region having a third layer thickness substantially equal to the first and second layer thicknesses.

Abstract: Disclosed is a method for generating an oscillating signal and an oscillator circuit.

Abstract: A method for transmitting data in a direction of transmission of a clock signal, wherein positive and negative edges of the clock signal are transmitted by pulses with opposite polarity, wherein the polarity of the pulses is not inverted when no data is transmitted, and wherein the polarity of at least one pulse is inverted when data is transmitted.

Abstract: A switching converter includes a transistor arrangement having a plurality of n transistors, with n?2, each including a gate terminal, and a load path between a source and a drain terminal, and at least m, with m?n and m?1 of the n transistors having a control terminal. The control terminal of each of the m transistors is configured to receive a control signal that adjusts an activation state of the transistor. The load paths of the plurality of n transistors are connected in parallel to form a load path of the transistor arrangement. A drive circuit is configured to adjust the activation state of the m transistors.

Abstract: A rectifier circuit includes a bridge circuit configured to receive an alternating input signal. A parallel resonant circuit is coupled between the bridge circuit and an output. The circuit could also include a capacitive storage element coupled to the output and configured to provide an output signal.

Abstract: A method for sensing an output voltage in a voltage converter includes at least one switching element and a transformer. A voltage is sampled across an auxiliary winding or a signal obtained from the voltage across an auxiliary winding in order to obtain a plurality of samples after the at least one switching element has assumed a first operation state and until the auxiliary voltage reaches a predefined threshold. The auxiliary winding is inductively coupled with the transformer. At least one sample obtained is evaluated before the auxiliary voltage reaches the predefined threshold.

Abstract: A transformer arrangement for signal transmission is provided, the transformer arrangement having at least one transformer with a primary coil and a secondary coil and a controller. The controller is configured in a magnetization phase to control a first current to flow through the primary coil to increase until a predefined criterion is fulfilled, wherein the magnetization phase is longer than a time constant of the primary coil of the at least one transformer. The controller is configured in a voltage application phase to apply a voltage to the at least one transformer so that a second current flows through the primary coil, wherein the second current has a polarity which changes during the voltage application phase compared with the first current, wherein the voltage application phase is shorter than two times the time constant of the primary coil of the at least one transformer.