Patents by Inventor Martin M. Frank

Martin M. Frank has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190131383
    Abstract: Artificial synaptic devices with an HfO2-based ferroelectric layer that can be implemented in the CMOS back-end are provided. In one aspect, an artificial synapse element is provided. The artificial synapse element includes: a bottom electrode; a ferroelectric layer disposed on the bottom electrode, wherein the ferroelectric layer includes an HfO2-based material that crystallizes in a ferroelectric phase at a temperature of less than or equal to about 400° C.; and a top electrode disposed on the bottom electrode. An artificial synaptic device including the present artificial synapse element and methods for formation thereof are also provided.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 2, 2019
    Inventors: Martin M. Frank, Takashi Ando, Xiao Sun, Jin Ping Han, Vijay Narayanan
  • Publication number: 20190131407
    Abstract: Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 2, 2019
    Inventors: Martin M. Frank, Takashi Ando, Xiao Sun, Jin Ping Han, Vijay Narayanan
  • Publication number: 20190130259
    Abstract: Neural networks include neuron layers arranged in order from an input neuron layer to an output neuron layer, with at least one hidden layer between them. Weight arrays between respective pairs of neuron layers each include controllable resistance elements and AND gates configured to control addressing of the plurality of controllable resistance elements. Each controllable resistance element includes a junction field effect transistor configured to provide a resistance on a signal line and a first pass transistor configured to apply a charge increment or decrement to the junction field effect transistor responsive to a control pulse, such that the resistance on the signal line changes. The control pulse is only passed to a controllable resistance element when a respective AND gate is triggered. A training module is configured to train the neural network by adjusting resistances of the plurality of controllable resistance elements in each of the weight arrays.
    Type: Application
    Filed: December 26, 2018
    Publication date: May 2, 2019
    Inventors: Stephen W. Bedell, Martin M. Frank, Devendra K. Sadana
  • Patent number: 10262999
    Abstract: An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Martin M. Frank, Pranita Kerber, Vijay Narayanan
  • Patent number: 10243143
    Abstract: A method of making a carbon nanotube structure includes depositing a first oxide layer on a substrate and a second oxide layer on the first oxide layer; etching a trench through the second oxide layer; removing end portions of the first oxide layer and portions of the substrate beneath the end portions to form cavities in the substrate; depositing a metal in the cavities to form first body metal pads; disposing a carbon nanotube on the first body metal pads and the first oxide layer such that ends of the carbon nanotube contact each of the first body metal layers; depositing a metal to form second body metal pads on the first body metal pads at the ends of the carbon nanotube; and etching to release the carbon nanotube, first body metal pads, and second body metal pads from the substrate, first oxide layer, and second oxide layer.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin M. Frank, Shu-Jen Han, George S. Tulevski
  • Publication number: 20190067413
    Abstract: A tapered metal nitride structure having a gentle sloping (i.e., tapered) sidewall is provided that includes an oxygen rich metal nitride portion located between each metal nitride portion of a stack of metal nitride portions. The structure is formed by incorporating/introducing oxygen into an upper portion of a first metal nitride layer to form an oxygen rich metal nitride surface layer. A second nitride is then formed atop the oxygen rich metal nitride surface layer. The steps of oxygen incorporation/addition and nitride layer formation may be repeated any number of times. An etch mask is then provided and thereafter a sputter etch is performed to provide the tapered metal nitride structure. The tapered metal nitride structure may be used as an electrode in a semiconductor device.
    Type: Application
    Filed: October 30, 2018
    Publication date: February 28, 2019
    Inventors: Martin M. Frank, Hiroyuki Miyazoe, Vijay Narayanan
  • Patent number: 10217745
    Abstract: An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Martin M. Frank, Pranita Kerber, Vijay Narayanan
  • Patent number: 10205097
    Abstract: Dielectric treatments for carbon nanotube devices are provided. In one aspect, a method for forming a carbon nanotube-based device is provided. The method includes: providing at least one carbon nanotube disposed on a first dielectric; removing contaminants from surfaces of the first dielectric; and depositing a second dielectric onto the first dielectric and at least partially surrounding the at least one carbon nanotube. A carbon nanotube-based device is also provided.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: February 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Damon B. Farmer, Martin M. Frank, Shu-Jen Han
  • Patent number: 10170550
    Abstract: A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second semiconductor material portions are removed selective to the first semiconductor material portions to form suspended semiconductor nanowires. Isolated gate structures are formed in regions underlying the disposable gate structure by deposition and recessing of a first gate dielectric layer and a first gate conductor layer. After formation of a gate spacer, source regions, and drain regions, raised source and drain regions are formed on the source regions and the drain regions by selective deposition of a semiconductor material. The disposable gate structure is replaced with a replacement gate structure by deposition and patterning of a second gate dielectric layer and a second gate conductor layer. Distortion of the suspended semiconductor nanowires is prevented by the disposable gate structure and the isolated gate structures.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Frank, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10147782
    Abstract: A tapered metal nitride structure having a gentle sloping (i.e., tapered) sidewall is provided that includes an oxygen rich metal nitride portion located between each metal nitride portion of a stack of metal nitride portions. The structure is formed by incorporating/introducing oxygen into an upper portion of a first metal nitride layer to form an oxygen rich metal nitride surface layer. A second nitride is then formed atop the oxygen rich metal nitride surface layer. The steps of oxygen incorporation/addition and nitride layer formation may be repeated any number of times. An etch mask is then provided and thereafter a sputter etch is performed to provide the tapered metal nitride structure. The tapered metal nitride structure may be used as an electrode in a semiconductor device.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: December 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Frank, Hiroyuki Miyazoe, Vijay Narayanan
  • Patent number: 10141333
    Abstract: A ferroelectric device includes a first electrode and a second electrode that each comprise one or more electrically conductive layers. The ferroelectric device also includes a layer of ferroelectric material disposed between, and in electrical communication with, the first electrode and the second electrode. The first electrode and/or the second electrode include a recessed region and the layer of ferroelectric material includes a corresponding region of increased thickness that resists polarity changes. For example, a programming signal that is applied across the first and second electrodes may change a polarity of one or more other portions of the layer of ferroelectric material without changing a polarity of a portion of the layer of ferroelectric material that is proximate to the region of increased thickness. A corresponding method is also disclosed herein.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: November 27, 2018
    Assignee: International Business Machines Corporation
    Inventor: Martin M. Frank
  • Publication number: 20180308845
    Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A gate dielectric layer is formed over one or more of the first and second channel regions. A nitrogen-containing layer is formed on the gate dielectric layer. A gate is formed on the gate dielectric.
    Type: Application
    Filed: June 19, 2018
    Publication date: October 25, 2018
    Inventors: Takashi Ando, Martin M. Frank, Renee T. Mo, Vijay Narayanan, John Rozen
  • Publication number: 20180308844
    Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A nitrogen-containing layer is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.
    Type: Application
    Filed: June 19, 2018
    Publication date: October 25, 2018
    Inventors: Takashi Ando, Martin M. Frank, Renee T. Mo, Vijay Narayanan, John Rozen
  • Patent number: 10109336
    Abstract: A ferroelectric device includes a first electrode and a second electrode that each comprise one or more electrically conductive layers. The ferroelectric device also includes a layer of ferroelectric material disposed between, and in electrical communication with, the first electrode and the second electrode. In some embodiments, the first electrode and/or the second electrode include a stepped vertical protrusion that protrudes into the layer of ferroelectric material. In certain embodiments, the layer of ferroelectric material comprises a region of reduced lateral width. The region of reduced lateral width and/or the stepped vertical protrusion enables changing a polarity of a portion of the ferroelectric material that is proximate to those features, in response to a programming signal applied across the first and second electrodes, without changing a polarity of one or more other portions of the layer of ferroelectric material. A corresponding method is also disclosed herein.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: October 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Frank, Jonathan Z. Sun
  • Patent number: 10062693
    Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A nitrogen-containing layer is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: August 28, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Martin M. Frank, Renee T. Mo, Vijay Narayanan, John Rozen
  • Patent number: 10062694
    Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A gate dielectric layer is formed over one or more of the first and second channel regions. A nitrogen-containing layer is formed on the gate dielectric layer. A gate is formed on the gate dielectric.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: August 28, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Martin M. Frank, Renee T. Mo, Vijay Narayanan, John Rozen
  • Publication number: 20180240799
    Abstract: An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.
    Type: Application
    Filed: April 23, 2018
    Publication date: August 23, 2018
    Inventors: Takashi Ando, Martin M. Frank, Pranita Kerber, Vijay Narayanan
  • Publication number: 20180225565
    Abstract: Controllable resistance elements and methods of setting the same include a junction field effect transistor configured to provide a resistance on a signal line. A first pass transistor is configured to apply a charge increment or decrement to the junction field effect transistor responsive to a control pulse, such that the resistance on the signal line changes.
    Type: Application
    Filed: February 6, 2017
    Publication date: August 9, 2018
    Inventors: Stephen W. Bedell, Martin M. Frank, Devendra K. Sadana
  • Publication number: 20180225567
    Abstract: Methods of training a neural network include applying an input signal to an array of weights to generate weighted output signals based on resistances of respective weights in the array of weights. A difference between the weighted output signals and a predetermined expected output is determined. Weights in the array of weights are set by applying a pulse to a controllable resistance element in each weight. The pulse increments or decrements a charge on a junction field effect transistor in the respective controllable resistance element.
    Type: Application
    Filed: November 3, 2017
    Publication date: August 9, 2018
    Inventors: Stephen W. Bedell, Martin M. Frank, Devendra K. Sadana
  • Patent number: 10014371
    Abstract: A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second semiconductor material portions are removed selective to the first semiconductor material portions to form suspended semiconductor nanowires. Isolated gate structures are formed in regions underlying the disposable gate structure by deposition and recessing of a first gate dielectric layer and a first gate conductor layer. After formation of a gate spacer, source regions, and drain regions, raised source and drain regions are formed on the source regions and the drain regions by selective deposition of a semiconductor material. The disposable gate structure is replaced with a replacement gate structure by deposition and patterning of a second gate dielectric layer and a second gate conductor layer. Distortion of the suspended semiconductor nanowires is prevented by the disposable gate structure and the isolated gate structures.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Frank, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek