Patents by Inventor Martin Rack

Martin Rack has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240101521
    Abstract: The present invention relates to diaminotriazine compounds and to their use as herbicides. It also relates to agrochemical compositions for crop protection and to a method for controlling unwanted vegetation.
    Type: Application
    Filed: January 17, 2022
    Publication date: March 28, 2024
    Inventors: Danny Geerdink, Matthias Witschel, Veronica Lopez Carrillo, Martin Hartmueller, Michael Rack, Desislava Slavcheva Petkova, Trevor William Newton, Sandra Lange, Thomas Seitz
  • Publication number: 20230411309
    Abstract: A structure for an RF device provided with a semiconductor region coated with a heterogeneous dielectric region, the heterogeneous dielectric region including, in at least one first direction parallel to a main plane of the substrate, an alternation of first areas made of a first dielectric material with positive fixed charges and of second dielectric areas made of a second dielectric material with negative fixed charge in order to create an alternation of polarity allowing preventing the formation of a parasitic conduction layer in the semiconductor region.
    Type: Application
    Filed: June 19, 2023
    Publication date: December 21, 2023
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, UNIVERSITE CATHOLIQUE DE LOUVAIN
    Inventors: Louis HUTIN, Maxime MOULIN, Thibaud FACHE, Christophe PLANTIER, Jean-Pierre RASKIN, Martin RACK
  • Patent number: 11222944
    Abstract: An integrated circuit device includes a semiconductor substrate having a resistivity of at least 100 ?·cm. An electrically insulating layer contacts the semiconductor substrate. The electrically insulating layer is susceptible of inducing in the semiconductor substrate a parasitic surface conduction layer that interfaces with the electrically insulating layer. An electrical circuit is located on the electrically insulating layer. The electrical circuit includes a section capable of inducing an electrical field in the semiconductor substrate. The integrated circuit device includes a depletion-inducing junction of which at least a portion is comprised in the semiconductor substrate. The depletion-inducing junction can autonomously induce in the semiconductor substrate a depleted zone that interfaces with a section of the electrically insulating layer that lies in-between two sections of the electrical circuit.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: January 11, 2022
    Assignee: UNIVERSITE CATHOLIQUE DE LOUVAIN
    Inventors: Jean-Pierre Raskin, Martin Rack
  • Publication number: 20210118977
    Abstract: An integrated circuit device includes a semiconductor substrate having a resistivity of at least 100 ?·cm. An electrically insulating layer contacts the semiconductor substrate. The electrically insulating layer is susceptible of inducing in the semiconductor substrate a parasitic surface conduction layer that interfaces with the electrically insulating layer. An electrical circuit is located on the electrically insulating layer. The electrical circuit includes a section capable of inducing an electrical field in the semiconductor substrate. The integrated circuit device includes a depletion-inducing junction of which at least a portion is comprised in the semiconductor substrate. The depletion-inducing junction can autonomously induce in the semiconductor substrate a depleted zone that interfaces with a section of the electrically insulating layer that lies in-between two sections of the electrical circuit.
    Type: Application
    Filed: May 2, 2019
    Publication date: April 22, 2021
    Applicant: UNIVERSITE CATHOLIQUE DE LOUVAIN
    Inventors: Jean-Pierre RASKIN, Martin RACK
  • Patent number: 10819282
    Abstract: A method for minimizing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer, wherein a curve representing the distortion as a function of a power of the input or output signal exhibits a trough around a given power (PDip), the method comprises applying, between the radiofrequency circuit and the semiconductor substrate, an electrical potential difference (VGB) chosen so as to move the trough toward a given operating power of the radiofrequency circuit.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: October 27, 2020
    Assignee: Soitec
    Inventors: Marcel Broekaart, Frederic Allibert, Eric Desbonnets, Jean-Pierre Raskin, Martin Rack
  • Publication number: 20200169222
    Abstract: A method for minimizing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer, wherein a curve representing the distortion as a function of a power of the input or output signal exhibits a trough around a given power (PDip), the method comprises applying, between the radiofrequency circuit and the semiconductor substrate, an electrical potential difference (VGB) chosen so as to move the trough toward a given operating power of the radiofrequency circuit.
    Type: Application
    Filed: May 23, 2018
    Publication date: May 28, 2020
    Inventors: Marcel Broekaart, Frederic Allibert, Eric Desbonnets, Jean-Pierre Raskin, Martin Rack