Abstract: A decimal floating-point instruction is executed in a round-for-reround mode. The decimal floating-point instruction is configured to perform a decimal floating-point operation on a decimal floating-point operand. The executing includes forming based on performing the decimal floating-point operation, an intermediate result having a high order portion and a low order portion. The high order portion has a least significant digit. A rounded-for-reround number is created from the intermediate result. The rounded-for-reround number includes the high order portion of the intermediate result and based on the least significant coefficient digit of the high order portion being a selected value and based on the low order portion having another selected value, the least significant digit of the rounded-for-reround number is incremented. The rounded-for-reround number is stored.

Abstract: An instruction is executed in round-for-reround mode wherein the permissible resultant value that is closest to and no greater in magnitude than the infinitely precise result is selected. If the selected value is not exact and the units digit of the selected value is either 0 or 5, then the digit is incremented by one and the selected value is delivered. In all other cases, the selected value is delivered.

Abstract: An instruction is executed in round-for-reround mode wherein the permissible resultant value that is closest to and no greater in magnitude than the infinitely precise result is selected. If the selected value is not exact and the units digit of the selected value is either 0 or 5, then the digit is incremented by one and the selected value is delivered. In all other cases, the selected value is delivered.

Abstract: A mechanism for executing fixed point divide operations using a floating point multiply-add pipeline are provided. With the mechanism, the floating point execution unit in a processor is modified to include elements that may be used to perform fixed point divide operations. These additional elements include a leading zero counter, a leading one counter, an estimate table unit, and a state machine. The fixed point divide operands are converted to a floating point format and an estimate of the reciprocal of the divisor is generated using estimate tables. These values are used in multiple passes through the floating point unit for calculating estimates of the quotient and corresponding error values. The estimates of the quotient are based on previous estimates of the quotient in a prior pass through the floating point unit and a corresponding error value. The final quotient estimate is truncated.

Abstract: A system for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal but is much greater than the product of operands A and C, i.e. AC. By limiting the additional shift of B during normalization, by the number of leading zeros in opB, no increase is needed in the output bus of the alignment shifter. Furthermore, the additional shift may be done either in the alignment shifter, or postponed to a later stage in the pipeline, where the result is normalized.

Abstract: A method of discovering a fault in a circuit is disclosed. The method comprises generating a first result of a selected function by performing the selected function on an operand, wherein the selected function employs a mask. Once the function is performed, an antimask of the mask is created, and the modulo of the antimask is calculated. A modulo function of the first result of the selected function is calculated to obtain a third result. A modulo of the operand is then calculated to obtain a fourth result, and a second function is then performed on the second result and the third result to obtain a fifth result. In response to comparing the fifth result to the fourth result, a signal is propagated to indicate a fault in the circuit.

Abstract: A system for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal but is much greater than the product of operands A and C, i.e. AC. By limiting the additional shift of B during normalization, by the number of leading zeros in opB, no increase is needed in the output bus of the alignment shifter. Furthermore, the additional shift may be done either in the alignment shifter, or postponed to a later stage in the pipeline, where the result is normalized.

Abstract: A method for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal but is much greater than the product of operands A and C, i.e. AC. By limiting the additional shift of B during normalization, by the number of leading zeros in opB, no increase is needed in the output bus of the alignment shifter. Furthermore, the additional shift may be done either in the alignment shifter, or postponed to a later stage in the pipeline, where the result is normalized.

Abstract: A system and method for executing fixed point divide operations using a floating point multiply-add pipeline are provided. With the system and method, the floating point execution unit in a processor is modified to include elements that may be used to perform fixed point divide operations. These additional elements include a leading zero counter, a leading one counter, an estimate table unit, and a state machine. The fixed point divide operands are converted to a floating point format and an estimate of the reciprocal of the divisor is generated using estimate tables. These values are used in multiple passes through the floating point unit for calculating estimates of the quotient and corresponding error values. The estimates of the quotient are based on previous estimates of the quotient in a prior pass through the floating point unit and a corresponding error value. The final quotient estimate is truncated.

Abstract: A method of discovering a fault in a circuit is disclosed. The method comprises generating a first result of a selected function by performing the selected function on an operand, wherein the selected function employs a mask. Once the function is performed, an antimask of the mask is created, and the modulo of the antimask is calculated. A modulo function of the first result of the selected function is calculated to obtain a third result. A modulo of the operand is then calculated to obtain a fourth result, and a second function is then performed on the second result and the third result to obtain a fifth result. In response to comparing the fifth result to the fourth result, a signal is propagated to indicate a fault in the circuit.

Abstract: A method of discovering a fault in a circuit is disclosed. The method comprises generating a first result of a selected function by performing the selected function on an operand, wherein the selected function employs a mask. Once the function is performed, an antimask of the mask is created, and the modulo of the antimask is calculated. A modulo function of the first result of the selected function is calculated to obtain a third result. A modulo of the operand is then calculated to obtain a fourth result, and a second function is then performed on the second result and the third result to obtain a fifth result. In response to comparing the fifth result to the fourth result, a signal is propagated to indicate a fault in the circuit.

Abstract: During execution of floating point convert to integer instructions, the necessity for incrementing the instruction result during rounding is predicted early and utilized to predict the result sign, to produce an implied bit which will achieve the correct result with round determination logic for standard floating point instructions, and to set up rounding mode, guard and sticky bits allowing the standard round determination logic to be utilized during rounding of the floating point convert to integer instruction result. The minimum logic required to control incrementing of a standard floating point instruction result during rounding may therefore be reused for floating point convert to integer instructions without increasing the critical path for rounding and without significantly adding to the complexity of the floating point execution unit.

Abstract: An improved method of estimating the square root, reciprocal square root, and reciprocal of an input value in a computer system. The input value, after being normalized, is used to select a pair of constants from a table. The constants are based on a linear approximation of the function for each interval of the input value, offset to reduce a maximum error value for a given interval. The estimated function is calculated by adding or subtracting the product of a part of the normalized input value and the first constant from the second constant. In one implementation, the input value is normalized within the range 1≦×<2, and one lookup table is used, having an interval size of {fraction (1/32)}. In a further preferred embodiment, only a lower order part of the mantissa is used in the multiply-add operation, to reduce the number of bits required (the high order part of the mantissa is used to select the constants from the table).

Abstract: A method for performing a logarithmic estimation on a positive floating-point number within a data processing system is disclosed. A floating-point number includes a sign bit, multiple exponent bits, and a mantissa having an implied one and multiple fraction bits. A fraction part of an estimate is obtained via a table lookup utilizing the fraction bits of the floating-point number as input. An integer part of the estimate is obtained by converting the exponent bits to an unbiased representation. The integer part is then concatenated with the fraction part to form an intermediate result. Subsequently, the intermediate result is normalized to yield a mantissa, and an exponent part is produced based on the normalization. Finally, the exponent part is combined with the mantissa to form a floating-point result.

Abstract: A method for performing a power of two estimation on a floating-point number within a data processing system is disclosed. The floating-point number includes a sign bit, multiple exponent bits, and a mantissa having an implied one and multiple fraction bits. In order to estimate the power of two of the floating-point number, the mantissa is partitioned into an integer part and a fraction part, based on the value of the exponent bits. A floating-point result is formed by assigning the integer part of the floating-point number as an unbiased exponent of the floating-point result, and by converting the fraction part of the floating-point number via a table lookup to become a fraction part of the floating-point result.

Abstract: An improved method of estimating the square root, reciprocal square root, and reciprocal of an input value in a computer system. The input value, after being normalized, is used to select a pair of constants from a table. The constants are based on a linear approximation of the function for each interval of the input value, offset to reduce a maximum error value for a given interval. The estimated function is calculated by adding or subtracting the product of a part of the normalized input value and the first constant from the second constant. In one implementation, the input value is normalized within the range 1.ltoreq.x<2, and one lookup table is used, having an interval size of 1/32. In a further preferred embodiment, only a lower order part of the mantissa is used in the multiply-add operation, to reduce the number of bits required (the high order part of the mantissa is used to select the constants from the table). In another implementation, the input value is normalized within the range 0.5.ltoreq.

Abstract: An apparatus and method reduces the number of rename registers for a floating point status and control register (FPSCR) in a superscalar microprocessor executing out of order/speculative instructions. A floating point queue (FPQ) receives speculative instructions and issues out-of-order instructions to FPQ execution units, each instruction containing a group identifier tag (GID) and a target identifier tag (TID). The GID tag indicates a set of instructions bounded by interruptible or branch instructions. The TID indicates a targeted architected facility and the program order of the instruction. The FPSCR contains status and control bits for each instruction and is updated when an instruction is executed and committed.

Abstract: A floating point arithmetic unit performs a multiply-add function B+(A*C) in which an alignment shifter is responsive to an input signal representative of the B mantissa. The shifter includes a sequential stack of multiplexers, typically three (3), for shifting the B mantissa to align it with the A*C product, and a complementer contained between two of the multiplexers to invert the signals when B is a negative number. A shift amount generator responsive to the A, B and C exponents produces control signals for the multiplexers. The shift amount generator includes a multiple input adder utilizing carry save adder and carry lookahead adder techniques to minimize delay, and separate decoders for each multiplexer or group of multiplexers. The generator also includes a Leading Zeros Anticipator (LZA) circuit for the most significant bits to limit shift amount signals that are within the shifting range of the shifter, which reduces the delay attributed to the carry lookahead adder.