Abstract: A photovoltaic semiconductor solar cell with a backside semiconductor-oxide-nitride-oxide nonvolatile charge storage structure (referred to as a “PHONOS solar cell”) is disclosed. The PHONOS solar cell includes a semiconductor surface region, a semiconductor bulk region, and a backside structure that includes the SONO nonvolatile charge storage structure and a backside contact. The backside SONO nonvolatile charge storage structure greatly improves solar cell efficiency gains by eliminating “backside” losses, i.e., losses due to the recombination of photo-generated minority charge carriers created by the incident sunlight. The PHONOS solar cell is a highly efficient, ultra-thin, semiconductor solar cell that can be manufactured at low cost.

Abstract: A photovoltaic semiconductor solar cell with a backside semiconductor-oxide-nitride-oxide nonvolatile charge storage structure (referred to as a “PHONOS solar cell”) is disclosed. The PHONOS solar cell includes a semiconductor surface region, a semiconductor bulk region, and a backside structure that includes the SONO nonvolatile charge storage structure and a backside contact. The backside SONO nonvolatile charge storage structure greatly improves solar cell efficiency gains by eliminating “backside” losses, i.e., losses due to the recombination of photo-generated minority charge carriers created by the incident sunlight. The PHONOS solar cell is a highly efficient, ultra-thin, semiconductor solar cell that can be manufactured at low cost.

Abstract: An addressable MNOS transistor structure is disclosed employing a plurality of gate regions between the source and drain diffusion regions of each transistor cell. The transistor cell is characterized by high and low threshold states which are settable by selective actuation of the corresponding plurality of gate regions. Reading of the state of the transistor is accomplished by applying a read voltage, having a value intermediate the two threshold values, to the corresponding plurality of gate regions and measuring whether or not an applied charge discharges from one diffusion region to the other.

Abstract: A method and apparatus for charge addressing a non-volatile MNOS memory cell in a LSI array of memory cells, is disclosed. Each MNOS cell of the array is made up of a substrate; adjacent diffusion areas in the substrate; a memory window intermediate the adjacent diffusion areas, controlled by a memory gate; and an enable gate adjacent the memory window and overlapping one of the diffusion areas. The memory gate and the enable gate are each separated from the substrate and each other by silicon dioxide/silicon nitride layers to provide a capacitive dielectric. Addressing of an individual cell in the array is achieved by selective activation of a corresponding enable gate and a corresponding memory gate, which are formed in an orthogonal grid array. The cell is accessed by a single stage of a shift register for both read and write operations through a transfer gating means.

Abstract: The proposed general-purpose, fully-analog device is capable of such functions as auto-correlation, cross-correlation, convolution, transversal filters, etc. at high speeds (one megahertz typical sample rates) with no analog-to-digital or digital-to-analog conversions. The device correlates analog samples in one CCD channel against analog samples in a second CCD channel by means of balanced MOSFET's which multiply the associated voltage samples to give current products that are summed for all multipliers. The two CCD channels include unique floating-clock sensor and buffer circuits which sense the CCD charge samples without affecting the efficiency of their propagation along the CCD shift register.

Abstract: A CCD focal plane processor having a plurality of columns of individual sensor elements with plural sensor elements per column. The structure includes plural CCD shift registers corresponding to the number of columns of sensors, each CCD shift register including a pair of stages corresponding to each of the element sensors of the corresponding column of the array. Two "snapshots" of the scene are taken at time-displaced intervals and are compared to detect differences therebetween to eliminate background, or unchanging scene content. The individual sensors provide outputs which are injected into the .alpha. stages of the corresponding paired shift register stages of each CCD shift register in a first time interval corresponding to the first "snapshot". The resulting charge packets in the first (.alpha.) stages then are advanced to the second (.beta.) stages of each shift register pair. The second "snapshot" corresponds to injecting a second signal into the .alpha. stages of the plurality of pairs of .alpha.

Abstract: "Progressive summation" of analog signals with a parallel-in/serial-out (P/I/SO) CCD structure replaces the conventional "simultaneous summation" of analog signals in serial-in/parallel-out (SI/PO) structured systems. Gain non-uniformities presented by buffer circuits and caused in part by threshold non-uniformities are avoided; on-chip power consumption is reduced, thereby avoiding a source of further exaggeration of gain non-uniformities of buffer circuits. Transversal filtering and correlation systems in accordance with the invention accordingly are achieved with these problems of prior art circuits avoided. Reduced power consumption on-chip also maintains more reasonable and constant operating temperature levels, avoiding deleterious effects of temperature increases on dynamic range of CCD systems due to leakage current levels which sharply increase with increased temperature, contributing noise and reducing the maximum charge potential of the CCD wells available for signal.