Patents by Inventor Marvin Wayne Martinez, Jr.

Marvin Wayne Martinez, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9256548
    Abstract: In one embodiment, rule-based virtual address translation is performed for accessing data (e.g., reading and/or writing data) typically stored in different manners and/or locations among one or more memories, such as, but not limited to, in packet switching devices. A virtual address is matched against a set of predetermined rules to identify one or more storing description parameters. These storing description parameters determine in which particular memory unit(s) and/or how the data is stored. Thus, different portions of a data structure (e.g., table) can be stored in different memories and/or using different storage techniques. The virtual address is converted to a lookup address based on the identified storing description parameter(s). One or more read or write operations in one or more particular memory units is performed based on the lookup address said converted from the virtual address.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: February 9, 2016
    Assignee: Cisco Technology, Inc.
    Inventors: Donald Edward Steiss, Marvin Wayne Martinez, Jr., John H. W. Bettink, John C. Carney, Mark Warden Hervin
  • Publication number: 20140149712
    Abstract: In one embodiment, rule-based virtual address translation is performed for accessing data (e.g., reading and/or writing data) typically stored in different manners and/or locations among one or more memories, such as, but not limited to, in packet switching devices. A virtual address is matched against a set of predetermined rules to identify one or more storing description parameters. These storing description parameters determine in which particular memory unit(s) and/or how the data is stored. Thus, different portions of a data structure (e.g., table) can be stored in different memories and/or using different storage techniques. The virtual address is converted to a lookup address based on the identified storing description parameter(s). One or more read or write operations in one or more particular memory units is performed based on the lookup address said converted from the virtual address.
    Type: Application
    Filed: November 29, 2012
    Publication date: May 29, 2014
    Inventors: Donald Edward Steiss, Marvin Wayne Martinez, JR., John H. W. Bettink, John C. Carney, Mark Warden Hervin
  • Patent number: 5860111
    Abstract: A write-back coherency system is used, in an exemplary embodiment, to implement write-back caching in an x86 processor installed in a multi-master computer system that does not support a write-back protocol for maintaining coherency between an internal cache and main memory during DMA operations. The write-back coherency system interrupts the normal bus arbitration operation to allow export of dirty data. In response to an arbitration-request (such as HOLD), if the internal cache contains dirty data, the processor is inhibited from providing arbitration-acknowledge (such as HLDA) until the dirty data is exported (the cache is dynamically switched to write-through mode to prevent data in the cache from being made dirty while the bus is arbitrated away). While the requesting bus master is accessing memory, bus snooping is performed and invalidation logic invalidates at least those cache locations corresponding to locations in memory that are affected by the requesting bus master.
    Type: Grant
    Filed: June 29, 1995
    Date of Patent: January 12, 1999
    Assignee: National Semiconductor Corporation
    Inventors: Marvin Wayne Martinez, Jr., Mark Bluhm, Jeffrey S. Byrne, David A. Courtright, Douglas Ewing Duschatko, Raul A. Garibay, Jr., Margaret R. Herubin
  • Patent number: 5664149
    Abstract: A write-back coherency system, including FLUSH/INVAL and LOCK protocols, is used, in an exemplary embodiment, in a microprocessor used in a computer system that selectively provides to the processor FLUSH and INVAL signals to implement a limited write-back protocol. The FLUSH/INVAL protocol is used by the computer system to control export and invalidate operations. In response to a FLUSH signal, the microprocessor exports dirty data from the cache. If INVAL is also asserted, the cache is also invalidated (i.e., if FLUSH is asserted and INVAL is not asserted, no invalidation is performed). With the LOCK protocol, LOCKed reads are serviced out of the cache for read hits--however, to maintain compatibility with computer systems that expect a LOCK operation to involve a read followed by a write access to external memory, the microprocessor will still run the external LOCKed read cycle, ignoring the returned data.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: September 2, 1997
    Assignee: Cyrix Corporation
    Inventors: Marvin Wayne Martinez, Jr., Mark W. Bluhm, Jeffrey S. Byrne, David A. Courtright, Douglas Ewing Duschatko, Raul A. Garibay, Jr., Margaret R. Herubin