Abstract: An electronic circuit comprising: an integrated circuit chip, the integrated circuit chip having a top face; portions of the top face of the chip being covered by a first metal layer electrically connected to the integrated circuit; and a dialectic layer formed on the top face of the chip beside and on top of said first metal layer; wherein the dielectric layer extends parallel to the top face of the chip beyond the edges of the chip, the first metal layer extending in the dielectric layer beyond the edges of the chip; and wherein portions of a top surface of the dielectric layer are covered by a second metal layer, portions of the first and second metal layers being electrically connected through the dielectric layer.

Abstract: An electronic circuit comprising: an integrated circuit chip, the integrated circuit chip having a top face; portions of the top face of the chip being covered by a first metal layer electrically connected to the integrated circuit; and a dielectic layer formed on the top face of the chip beside and on top of said first metal layer; wherein the dielectric layer extends parallel to the top face of the chip beyond the edges of the chip, the first metal layer extending in the dielectric layer beyond the edges of the chip; and wherein portions of a top surface of the dielectric layer are covered by a second metal layer, portions of the first and second metal layers being electrically connected through the dielectric layer.

Abstract: A method and apparatus for depositing self-aligned base contacts where over-etching the emitter sidewall to undercut the emitter contact is not needed. A semiconductor structure has a T-shaped emitter contact that comprises a T-top and T-foot. The T-top acts as a mask for depositing the base contacts. In forming the T-top, its dimensions may be varied, thereby allowing the spacing between the base contacts and emitter to be adjusted.

Abstract: A method is provided for improving edge terminations in a semiconductor device while maintaining breakdown voltage of said semiconductor device at or near its theoretical limit. The method comprises: employing ion-implantation to create a compensated region around the semiconductor device, followed by wet chemical etching to form a mesa on the order of 0.2 to 0.3 &mgr;m. The method provides a simple but novel approach to fabricate edge terminations in semiconductor devices in general and in devices employing p-n junctions such as in a GaAs heterojunction bipolar transistor (HBT) to achieve near-ideal electrical characteristics at the device edge. Instead of traditional edge beveling techniques such as those involving grinding, sandblasting, or mesa-etching using masks, the technique disclosed herein utilizes ion-implantation to create a compensated region around the device and wet chemical etching to make a shallow mesa.

Abstract: A method is provided for improving edge terminations in a semiconductor device while maintaining breakdown voltage of said semiconductor device at or near its theoretical limit. The method comprises: employing ion-implantation to create a compensated region around the semiconductor device, followed by wet chemical etching to form a mesa on the order of 0.2 to 0.3 &mgr;m. The method provides a simple but novel approach to fabricate edge terminations in semiconductor devices in general and in devices employing p-n junctions such as in a GaAs heterojunction bipolar transistor (HBT) to achieve near-ideal electrical characteristics at the device edge. Instead of traditional edge beveling techniques such as those involving grinding, sandblasting, or mesa-etching using masks, the technique disclosed herein utilizes ion-implantation to create a compensated region around the device and wet chemical etching to make a shallow mesa.