Patents by Inventor Masaaki Iwai

Masaaki Iwai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230031562
    Abstract: A semiconductor device includes a semiconductor package including an n-type channel normally-off transistor including a first electrode, a second electrode, and a first control electrode, a normally-on transistor including a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode, a first diode including a first anode electrically connected to the second control electrode and a first cathode electrically connected to the third electrode, and a Zener diode including a second anode electrically connected to the first electrode and a second cathode electrically connected to the second electrode; a first terminal provided on the semiconductor package, the first terminal being electrically connected to the first electrode; a plurality of second terminals provided on the semiconductor package, the second terminals being electrically connected to the first electrode, and the second terminals being lined up in a first direction; a third terminal provided on t
    Type: Application
    Filed: October 18, 2022
    Publication date: February 2, 2023
    Inventors: Toru Sugiyama, Akira Yoshioka, Hung Hung, Yasuhiro Isobe, Hitoshi Kobayashi, Tetsuya Ohno, Naonori Hosokawa, Masaaki Onomura, Masaaki Iwai
  • Patent number: 11508647
    Abstract: A semiconductor device includes a semiconductor package including an n-type channel normally-off transistor, a normally-on transistor, a first diode, and a Zener diode; a first terminal provided on the semiconductor package; a plurality of second terminals provided on the semiconductor package, and the second terminals being lined up in a first direction; a third terminal provided on the semiconductor package; a plurality of fourth terminals provided on the semiconductor package; and a plurality of fifth terminals provided on the semiconductor package, and the fifth terminals being lined up in the first direction.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: November 22, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Toru Sugiyama, Akira Yoshioka, Hung Hung, Yasuhiro Isobe, Hitoshi Kobayashi, Tetsuya Ohno, Naonori Hosokawa, Masaaki Onomura, Masaaki Iwai
  • Publication number: 20220140731
    Abstract: A semiconductor device according to embodiments includes a normally-off transistor having a first electrode, a second electrode, and a first control electrode, a normally-on transistor having a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode, a first element having a first end portion electrically connected to the first control electrode and a second end portion electrically connected to the first electrode, and the first element including a first capacitance component; and, a second element having a third end portion electrically connected to the first control electrode and the first end portion and a fourth end portion, and the second element including a second capacitance component, wherein, when a threshold voltage of the normally-off transistor is denoted by Vth, a maximum rated gate voltage of the normally-off transistor is denoted by Vg_max, a voltage of the fourth end portion is denoted by Vg_on, the first capacitance component is deno
    Type: Application
    Filed: January 19, 2022
    Publication date: May 5, 2022
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Akira YOSHIOKA, Toru SUGIYAMA, Masaaki IWAI, Naonori HOSOKAWA, Masaaki ONOMURA, Hung HUNG, Yasuhiro ISOBE
  • Patent number: 11290100
    Abstract: Provided is a semiconductor device including a normally-off transistor having a first electrode, a second electrode, and a first control electrode, a normally-on transistor having a third electrode, a fourth electrode, and a second control electrode, a first capacitor having a first end and a second end, a Zener diode having a first anode and a first cathode, a first resistor having a third end and a fourth end, a first diode having a second anode and a second cathode, a second resistor having a fifth end and a sixth end, a second diode having a third anode and a third cathode, and a second capacitor having a seventh end and an eighth end.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: March 29, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hung Hung, Yasuhiro Isobe, Akira Yoshioka, Toru Sugiyama, Masaaki Iwai, Naonori Hosokawa, Masaaki Onomura, Hitoshi Kobayashi, Tetsuya Ohno
  • Publication number: 20220084916
    Abstract: A semiconductor device includes a semiconductor package including an n-type channel normally-off transistor including a first electrode, a second electrode, and a first control electrode, a normally-on transistor including a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode, a first diode including a first anode electrically connected to the second control electrode and a first cathode electrically connected to the third electrode, and a Zener diode including a second anode electrically connected to the first electrode and a second cathode electrically connected to the second electrode; a first terminal provided on the semiconductor package, the first terminal being electrically connected to the first electrode; a plurality of second terminals provided on the semiconductor package, the second terminals being electrically connected to the first electrode, and the second terminals being lined up in a first direction; a third terminal provided on t
    Type: Application
    Filed: March 10, 2021
    Publication date: March 17, 2022
    Inventors: Toru Sugiyama, Akira Yoshioka, Hung Hung, Yasuhiro Isobe, Hitoshi Kobayashi, Tetsuya Ohno, Naonori Hosokawa, Masaaki Onomura, Masaaki Iwai
  • Publication number: 20220077131
    Abstract: A semiconductor device according to an embodiment includes: a first nitride semiconductor layer having a first surface and a second surface; a first source electrode provided on the first surface; a first drain electrode provided on the first surface; a first gate electrode provided on the first surface between the first source electrode and the first drain electrode; a second nitride semiconductor layer having a third surface and a fourth surface, the third surface being provided on the second surface and facing the second surface, and the second nitride semiconductor layer having a smaller band gap than the first nitride semiconductor layer; and a first semiconductor device having a fifth surface provided on the fourth surface and facing the fourth surface with a size equal to or smaller than a size of the fourth surface, the first semiconductor device including a first semiconductor material having a smaller band gap than the second nitride semiconductor layer.
    Type: Application
    Filed: September 7, 2021
    Publication date: March 10, 2022
    Inventors: Yasuhiro ISOBE, Hung HUNG, Akira YOSHIOKA, Toru SUGIYAMA, Hitoshi KOBAYASHI, Tetsuya OHNO, Masaaki IWAI, Naonori HOSOKAWA, Masaaki ONOMURA
  • Patent number: 11264899
    Abstract: A semiconductor device according to embodiments includes a normally-off transistor having a first electrode, a second electrode, and a first control electrode, a normally-on transistor having a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode, a first element having a first end portion electrically connected to the first control electrode and a second end portion electrically connected to the first electrode, and the first element including a first capacitance component; and, a second element having a third end portion electrically connected to the first control electrode and the first end portion and a fourth end portion, and the second element including a second capacitance component, wherein, when a threshold voltage of the normally-off transistor is denoted by Vth, a maximum rated gate voltage of the normally-off transistor is denoted by Vg_max, a voltage of the fourth end portion is denoted by Vg_on, the first capacitance component is deno
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: March 1, 2022
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Akira Yoshioka, Toru Sugiyama, Masaaki Iwai, Naonori Hosokawa, Masaaki Onomura, Hung Hung, Yasuhiro Isobe
  • Publication number: 20210194475
    Abstract: Provided is a semiconductor device including: a normally-off transistor having a first electrode, a second electrode, and a first control electrode; a normally-on transistor having a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode; a first capacitor having a first end and a second end electrically connected to the second control electrode; a Zener diode having a first anode and a first cathode, the first anode being electrically connected to the second end and the second control electrode, and the first cathode being electrically connected to the third electrode; a first resistor having a third end and a fourth end electrically connected to the first control electrode; a first diode having a second anode and a second cathode, the second anode being electrically connected to the third end; a second resistor having a fifth end electrically connected to the second cathode and a sixth end electrically connected to the fourth end and the first cont
    Type: Application
    Filed: September 4, 2020
    Publication date: June 24, 2021
    Inventors: Hung Hung, Yasuhiro Isobe, Akira Yoshioka, Toru Sugiyama, Masaaki Iwai, Naonori Hosokawa, Masaaki Onomura, Hitoshi Kobayashi, Tetsuya Ohno
  • Patent number: 10998433
    Abstract: A semiconductor device of an embodiment includes a first nitride semiconductor layer; a second nitride semiconductor layer placed on the first nitride semiconductor layer; a first electrode placed on the second nitride semiconductor layer; a second electrode placed on the first nitride semiconductor layer; a gate electrode placed between the first electrode and the second electrode; a first field plate electrode placed on the second nitride semiconductor layer, the first field plate electrode having the same height as the gate electrode; and a second field plate electrode provided on an upper side of the first field plate electrode, the second field plate electrode being placed on a side of the second electrode compared to the first field plate electrode.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: May 4, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hung Hung, Yasuhiro Isobe, Akira Yoshioka, Toru Sugiyama, Masaaki Iwai, Naonori Hosokawa, Masaaki Onomura
  • Publication number: 20210083577
    Abstract: A semiconductor device according to embodiments includes a normally-off transistor having a first electrode, a second electrode, and a first control electrode, a normally-on transistor having a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode, a first element having a first end portion electrically connected to the first control electrode and a second end portion electrically connected to the first electrode, and the first element including a first capacitance component; and, a second element having a third end portion electrically connected to the first control electrode and the first end portion and a fourth end portion, and the second element including a second capacitance component, wherein, when a threshold voltage of the normally-off transistor is denoted by Vth, a maximum rated gate voltage of the normally-off transistor is denoted by Vg_max, a voltage of the fourth end portion is denoted by Vg_on, the first capacitance component is deno
    Type: Application
    Filed: January 17, 2020
    Publication date: March 18, 2021
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Akira YOSHIOKA, Toru SUGIYAMA, Masaaki IWAI, Naonori HOSOKAWA, Masaaki ONOMURA, Hung HUNG, Yasuhiro ISOBE
  • Patent number: 10868163
    Abstract: A semiconductor device includes first and second nitride semiconductor layers, a first electrode electrically connected to the first nitride semiconductor layer, a second electrode electrically connected to the first nitride semiconductor layer, a gate electrode between the first and second electrodes, a first field plate electrode electrically connected to the first electrode, a second field plate electrode between the gate electrode and the second electrode and electrically connected to the first electrode, a first conductive layer on the gate electrode, and a second conductive layer on the first conductive layer. A distance between the gate electrode and the second field plate electrode in a lateral direction is shorter than a distance between the first conductive layer and the second field plate electrode in the lateral direction, and is equal to or shorter than a distance between the second conductive layer and the second field plate electrode.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: December 15, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hung Hung, Akira Yoshioka, Toru Sugiyama, Masaaki Iwai, Naonori Hosokawa
  • Publication number: 20200295171
    Abstract: A semiconductor device of an embodiment includes a first nitride semiconductor layer; a second nitride semiconductor layer placed on the first nitride semiconductor layer; a first electrode placed on the second nitride semiconductor layer; a second electrode placed on the first nitride semiconductor layer; a gate electrode placed between the first electrode and the second electrode; a first field plate electrode placed on the second nitride semiconductor layer, the first field plate electrode having the same height as the gate electrode; and a second field plate electrode provided on an upper side of the first field plate electrode, the second field plate electrode being placed on a side of the second electrode compared to the first field plate electrode.
    Type: Application
    Filed: September 3, 2019
    Publication date: September 17, 2020
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hung Hung, Yasuhiro Isobe, Akira Yoshioka, Toru Sugiyama, Masaaki Iwai, Naonori Hosokawa, Masaaki Onomura
  • Patent number: 10771057
    Abstract: A semiconductor device of embodiments includes a first normally-off transistor having a first electrode, a second electrode, and a first control electrode, a normally-on transistor having a third electrode electrically connected to the second electrode via a first wiring, a fourth electrode, and a second control electrode, a second normally-off transistor having a fifth electrode, a sixth electrode electrically connected to the third electrode via a second wiring, and a third control electrode, a first diode having a first anode electrically connected to the second control electrode and a first cathode electrically connected to the third electrode, and a capacitor having a first end portion connected to the first anode and the second control electrode and a second end portion.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: September 8, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Akira Yoshioka, Toru Sugiyama, Masaaki Iwai, Naonori Hosokawa, Masaaki Onomura, Hung Hung, Yasuhiro Isobe
  • Publication number: 20200091331
    Abstract: A semiconductor device includes first and second nitride semiconductor layers, a first electrode electrically connected to the first nitride semiconductor layer, a second electrode electrically connected to the first nitride semiconductor layer, a gate electrode between the first and second electrodes, a first field plate electrode electrically connected to the first electrode, a second field plate electrode between the gate electrode and the second electrode and electrically connected to the first electrode, a first conductive layer on the gate electrode, and a second conductive layer on the first conductive layer. A distance between the gate electrode and the second field plate electrode in a lateral direction is shorter than a distance between the first conductive layer and the second field plate electrode in the lateral direction, and is equal to or shorter than a distance between the second conductive layer and the second field plate electrode.
    Type: Application
    Filed: March 1, 2019
    Publication date: March 19, 2020
    Inventors: Hung HUNG, Akira YOSHIOKA, Toru SUGIYAMA, Masaaki IWAI, Naonori HOSOKAWA
  • Patent number: 10483061
    Abstract: A protection device including: (i) a protection component having a first thermal fuse and a resistive body, the resistive body being supplied with a current in an abnormal state to generate heat, the heat activating the first thermal fuse to cut off the current; (ii) a PTC component; and (iii) a second thermal fuse, the second thermal fuse being electrically connected in series to the PTC component, the first thermal fuse of the protection component being electrically connected in parallel to the PTC component and to the second thermal fuse, and the protection component being activated in the abnormal state so that the PTC component trips to generate heat, the heat blowing the second thermal fuse.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: November 19, 2019
    Assignee: LITTELFUSE JAPAN G.K.
    Inventors: Takayuki Yokota, Masaaki Iwai, Hirotsugu Takegawa, Naotaka Ikawa
  • Patent number: 10395877
    Abstract: The present invention proposes a protection device which has a large rated voltage and a large rated current, which is capable of sufficiently suppressing arc generation during activation, and which is also capable of providing suitable protection against overcurrent due to short circuiting or the like of a main circuit. The protection device of the present invention includes (i) a protection element which includes a first thermal fuse and a resistor, and in which the resistor generates heat as a result of current passing through the resistor when there are abnormalities, and the first thermal fuse is activated due to this heat and interrupts the current, (ii) a PTC element and a second thermal fuse which are electrically connected in parallel to the first thermal fuse and which are electrically connected in series to each other, and (iii) a current fuse which is electrically connected in series to the first thermal fuse.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: August 27, 2019
    Assignee: Littelfuse, Inc.
    Inventors: Masaaki Iwai, Takayuki Yokota
  • Patent number: 10396543
    Abstract: The present invention provides a protection device that can more surely protect an electronic or an electric apparatus even when an inrush current value is large and its magnitude has large dispersion, and that has a recovery property. The protection device of the present invention includes a PTC component; a resistive component; and a first terminal and a second terminal, wherein the first terminal, the PTC component, the resistive component, and the second terminal are electrically connected in series in this order.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: August 27, 2019
    Assignee: LITTELFUSE JAPAN G.K.
    Inventors: Arata Tanaka, Masaaki Iwai, Tsuyoshi Takizawa
  • Patent number: 10177505
    Abstract: A protective element including (i) a PTC element having an opening passing through in the thickness direction, and (ii) a first electrode and a second electrode positioned on both main surfaces of the PTC element, the protective element characterized in that the first electrode extends from a main surface of the PTC element over an edge thereof and into the opening wherein the PTC element is not prevented from expanding even when secured by a screw or caulking.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: January 8, 2019
    Assignee: LITTELFUSE JAPAN G.K.
    Inventors: Arata Tanaka, Masaaki Iwai, Toshiya Ikeno, Tsuyoshi Takizawa
  • Publication number: 20180082769
    Abstract: The present invention relates to a protective element which comprises a layered PTC element having a first main surface and a second main surface, a first electrode that is positioned on the first main surface of the PTC element and a second electrode that is positioned on the second main surface of the PTC element, and the protective element characterized in that at least a portion of the first electrode and at least a portion of the second electrode are positioned so as to oppose each other with the PTC element being interposed therebetween, and a portion of the first main surface is exposed.
    Type: Application
    Filed: April 22, 2016
    Publication date: March 22, 2018
    Applicant: Littelfuse Japan G.K.
    Inventors: Masaaki IWAI, Tsuyoshi TAKIZAWA
  • Publication number: 20180040443
    Abstract: The object of the present invention is to provide a protection device capable of sufficiently suppressing the occurrence of arc at the time of activation with large rated voltage and rated current, as well as capable of fully opening the circuit. The present invention provides a protection device comprising: (i) a protection component comprising a first thermal fuse and a resistive body, the resistive body being supplied with a current in an abnormal state to generate heat, the heat activating the first thermal fuse to cut off the current; (ii) a PTC component; and (iii) a second thermal fuse, the second thermal fuse being electrically connected in series to the PTC component, the first thermal fuse of the protection component being electrically connected in parallel to the PTC component and to the second thermal fuse, and the protection component being activated in the abnormal state so that the PTC component trips to generate heat, the heat blowing the second thermal fuse.
    Type: Application
    Filed: July 1, 2014
    Publication date: February 8, 2018
    Applicants: Tyco Electronics Japan G.K., Uchihashi Estec Co., Ltd.
    Inventors: Takayuki Yokota, Masaaki Iwai, Hirotsugu Takegawa, Naotaka Ikawa