Abstract: Embodiments of the disclosure provide systems and methods for using a PLL and a high frequency generator outside the loop to obtain the fmax of the divider. The divider in the PLL loop is fed by a VCO and its operation range is characterized by measuring the PLL lock range. An identical copy of the same divider is used outside the PLL loop and it is fed by a higher frequency clock. The high frequency clock is generated by the multiple phase of the VCO. By characterizing the outputs from both dividers, the fmax of the divider is obtained.

Abstract: Embodiments of the disclosure provide systems and methods for clock duty cycle measurement. A clock signal and a complement of the clock signal are provided to a charge pump during first and second predetermined timing windows. A charge pump is operable to generate first and second output voltages in response to the clock signal and the complement of the clock signal during the first and second timing windows, respectively. In addition a predetermined positive voltage and a ground voltage are applied to the charge pump during predetermined third and fourth timing windows, respectively. The charge pump is operable to generate third and fourth output voltage signals corresponding to the predetermined positive and ground voltages during the third and fourth timing windows, respectively. The first, second, third and fourth voltages are then used to calculate the duty cycle of the clock.

Abstract: A fuel cell vehicle is equipped with a power control unit which converts power supplied from the fuel cell and supplies that converted power to a load. High voltage wiring, which connects at least one of the fuel cell and the load to the power control unit, is provided on one side of either the left or the right side of a vehicle, and a fuel line for supplying a fuel gas to the fuel cell is provided on the other side of the vehicle, which is opposite the side on which the high voltage wiring is provided.

Abstract: Mechanisms are provided for compensating for process and temperature variations in a circuit. The mechanisms may select at least one resistor in a plurality of resistors in the circuit to provide a resistance value for generating a calibration voltage input to the circuit to compensate for variations in process. A reference signal may be compared to a feedback signal generated by the circuit based on the calibration signal. A determination is made as to whether the feedback signal is within a tolerance of the reference signal and, if so, an identifier of the selected at least one resistor is stored in a memory device coupled to the circuit. The circuit may be operated using the selected at least one resistor based on the identifier stored in the memory device. An apparatus and integrated circuit device utilizing these mechanisms are also provided.

Abstract: A deviation amount of a top position of a convex surface of a protruding portion formed on a flat member and a deepest position of a concave surface on the back side of the convex surface, is obtained in XY-coordinates in a plane parallel to an extension plane of the flat member. An annular image obtained by illuminating the concave surface is photographed, and the XY-coordinates of the deepest position of the concave surface are obtained based on the image thus obtained. Regarding the convex surface, the X-coordinate and the Y-coordinate of the top position of the convex surface are respectively obtained by a front camera having an image taking optical axis parallel to the extension plane of the flat member and a side camera having an image taking optical axis parallel to the plane and perpendicular to the image taking optical axis of the front camera, and the deviation amount and deviation direction are obtained based on their respective XY-coordinates obtained.

Abstract: A design structure for a programmable interpolative voltage controlled oscillator (VCO) with adjustable frequency range output is provided. Programmable delay cells whose size is modifiable based on control inputs to the programmable delay cells are utilized. A different set of control inputs may be provided to programmable delay cells of an inner sub-ring from the set of control inputs provided to programmable delay cells of a main ring of the VCO. The minimum frequency output of the VCO is governed by the main ring programmable delay cell strength with the maximum frequency output of the VCO being governed by a ratio of strengths of the main ring programmable delay cells to the inner sub-ring programmable delay cell. By modifying the control inputs to the inner sub-ring and main ring programmable delay cells, the minimum and maximum frequency outputs, and thus the range between these two frequency outputs, are made programmable.

Abstract: An intake control device for a vehicle engine includes: a throttle body; a main throttle valve configured to be opened or closed in response to an operation applied to a throttle grip, the main throttle valve being rotatably supported by the throttle body; a sub-throttle valve configured to be opened or closed under control of an actuator, the sub-throttle valve being rotatably supported by the throttle body; an intake air path formed in the throttle body and provided with the main throttle valve and the sub-throttle valve so as to open or close the intake air path; and a bypass air path that is different from the intake air path and provided with an idle speed control (ISC) valve that is controlled so as to open or close the bypass air path in conjunction with the sub-throttle valve.

Abstract: Systems and methods for enabling the determination of voltage controlled oscillator (VCO) linearity, duty cycle determination and duty cycle correction in phase locked loop circuits (PLL's.) One embodiment comprises a method including the steps of determining the frequency response of a PLL's VCO as a function of duty cycle, applying a signal based on the VCO output to the VCO input, measuring the resulting frequency of the VCO output signal, determining the duty cycle corresponding to the measured frequency, and configuring a duty cycle correction unit correct the duty cycle of the VCO output signal to about 50%. Determining the frequency response of the VCO may include, for each of several different duty cycle values between 0% and 100%, applying the VCO input signal to the VCO and determining the corresponding frequency of the VCO output signal. This may also be done for duty cycles of 0% and 100%.

Abstract: A design structure for a circuit for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device is provided. The circuit has a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.

Abstract: An apparatus and method for obtaining a desired phase locked loop (PLL) duty cycle without a pre-scaler are provided. The PLL circuit of the illustrative embodiments utilizes two separate loops that simultaneously operate on the VCO. One loop ensures the frequency and phase lock while the other loop ensures the duty cycle lock. The VCO is modified to have an additional control port to adjust the duty cycle. Thus, the VCO has one control port for performing frequency adjustment and one control port for duty cycle adjustment. As a result, both the duty cycle and the frequency may be controlled using the VCO of the PLL circuit of the illustrative embodiments so as to achieve any desired duty cycle output without requiring a VCO pre-scaler circuit or duty cycle correction circuit.

Abstract: A method and apparatus for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device are provided. The mechanism employs a circuit having a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.

Abstract: A design structure for a circuit for obtaining a desired phase locked loop (PLL) duty cycle without a pre-scaler is provided. The PLL circuit of the illustrative embodiments utilizes two separate loops that simultaneously operate on the VCO. One loop ensures the frequency and phase lock while the other loop ensures the duty cycle lock. The VCO is modified to have an additional control port to adjust the duty cycle. Thus, the VCO has one control port for performing frequency adjustment and one control port for duty cycle adjustment. As a result, both the duty cycle and the frequency may be controlled using the VCO of the PLL circuit of the illustrative embodiments so as to achieve any desired duty cycle output without requiring a VCO pre-scaler circuit or duty cycle correction circuit.

Abstract: To provide mixing elements of a Kenix type static mixer capable of decreasing fluids remaining wastefully in a casing without elongation of the casing, the mixing elements are arranged in a casing so that end parts adjacent in an axial direction are connected to cross almost orthogonally, the mixing element includes a partition wall part (1) in a thin flat plate shape for partitioning the casing into approximately equal cross sectional areas, and plural spiral blade parts (2, . . . ) having a shape of a thin plate twisted by approximately 180 degrees, and being positioned in spaces partitioned by the partition wall part (1), wherein outer peripheries of the spiral blade parts (2, . . . ) at the partition wall part (1) side are integrally contacted with the partition wall part (1), and outer peripheries of the spiral blade parts (2, . . . ) at the casing side are contacted with an inner wall of the casing.

Abstract: A design structure for a circuit for measuring the absolute duty cycle of a signal, is provided. A non-inverted path from a signal source is selected and various DCC circuit setting indices are cycled through until a divider, coupled to the output of the DCC circuit, fails. A first minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of the failure. An inverted path from the signal source is selected and the various DCC circuit setting indices are cycled through again until the divider fails. A second minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of this second failure. The duty cycle is then calculated based on a difference of the first and second minimum pulse width values.

Abstract: A method and apparatus for measuring the absolute duty cycle of a signal are provided. A non-inverted path from a signal source is selected and various DCC circuit setting indices are cycled through until a divider, coupled to the output of the DCC circuit, fails. A first minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of the failure. An inverted path from the signal source is selected and the various DCC circuit setting indices are cycled through again until the divider fails. A second minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of this second failure. The duty cycle is then calculated based on a difference of the first and second minimum pulse width values.

Abstract: Systems and methods for conveying signals between integrated circuit (IC) components in domains having different supply voltages. AC coupling is used to increase the speed at which the common mode voltage of a signal is shifted from one level to another. One embodiment comprises a method for level shifting a binary signal in an IC. This method includes receiving an input binary signal and decoupling its AC component from its common mode component. A second common mode component is added to the AC component, providing a binary output signal. The common mode voltage of the input signal may be greater (or smaller) than that of the output signal. In one embodiment of the method, duty cycle compensation (DCC) is performed. The DCC drives the duty cycle toward a desired value.

Abstract: A PCU having an inverter and the like includes a connector electrically connecting the PCU and external equipment located outside the PCU, a safety bar attaching the connector for preventing the connector from being touched, and an ECU detecting that an interlock circuit is opened via an interlock signal line in response to detachment of the safety bar to shut off supply of electric power to the PCU.

Abstract: A programmable interpolative voltage controlled oscillator (VCO) with adjustable frequency range output is provided. With the VCO, programmable delay cells whose size is modifiable based on control inputs to the programmable delay cells are utilized. A different set of control inputs may be provided to programmable delay cells of an inner sub-ring from the set of control inputs provided to programmable delay cells of a main ring of the VCO. The minimum frequency output of the VCO is governed by the main ring programmable delay cell strength with the maximum frequency output of the VCO being governed by a ratio of strengths of the main ring programmable delay cells to the inner sub-ring programmable delay cell. By modifying the control inputs to the inner sub-ring and main ring programmable delay cells, the minimum and maximum frequency outputs, and thus the range between these two frequency outputs, are made programmable.

Abstract: An intake control device for a vehicle engine includes: a throttle body; a main throttle valve configured to be opened or closed in response to an operation applied to a throttle grip, the main throttle valve being rotatably supported by the throttle body; a sub-throttle valve configured to be opened or closed under control of an actuator, the sub-throttle valve being rotatably supported by the throttle body; an intake air path formed in the throttle body and provided with the main throttle valve and the sub-throttle valve so as to open or close the intake air path; and a bypass air path that is different from the intake air path and provided with an idle speed control (ISC) valve that is controlled so as to open or close the bypass air path in conjunction with the sub-throttle valve.

Abstract: Systems and methods for detecting the mode (a.k.a., state) of a fuse or set of fuses in a device such as an integrated circuit. One embodiment comprises a method for determining three fuse states (uncut, cut, and destroyed) by comparing the fuse voltage with two reference voltages. Each fuse state has a different (indicative) impedance and is associated with a fuse voltage. The fuse voltage is below, between, or above two reference voltages, thereby determining the fuse state. One embodiment includes the fuse in series with a read transistor as well as two reference voltage generators, each comprising a resistor and a transistor (equivalent to the read transistor). Both resistors' impedances are greater than the uncut fuse impedance and one is less than the cut fuse impedance. Two comparators are used to bracket the fuse voltage, indicating that the fuse is uncut, cut, or destroyed.