Patents by Inventor Masaaki Kuzuhara

Masaaki Kuzuhara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8653561
    Abstract: A III-nitride semiconductor electronic device comprises a semiconductor laminate provided on a primary surface of a substrate, a first electrode in contact with the semiconductor laminate, and a second electrode. The semiconductor laminate includes a channel layer and a barrier layer making a junction with the channel layer. The channel layer comprises first III-nitride semiconductor containing aluminum as a Group III constituent element, and the barrier layer comprises second III-nitride semiconductor containing aluminum as a Group III constituent element. The semiconductor laminate including first, second and third regions arranged along the primary surface, and the third region is located between the first region and the second region. The barrier layer includes first to third portions included in the first to third regions, respectively.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: February 18, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Hashimoto, Katsushi Akita, Yoshiyuki Yamamoto, Masaaki Kuzuhara, Norimasa Yafune
  • Publication number: 20110278647
    Abstract: A III-nitride semiconductor electronic device comprises a semiconductor laminate provided on a primary surface of a substrate, a first electrode in contact with the semiconductor laminate, and a second electrode. The semiconductor laminate includes a channel layer and a barrier layer making a junction with the channel layer. The channel layer comprises first III-nitride semiconductor containing aluminum as a Group III constituent element, and the barrier layer comprises second III-nitride semiconductor containing aluminum as a Group III constituent element. The semiconductor laminate including first, second and third regions arranged along the primary surface, and the third region is located between the first region and the second region. The barrier layer includes first to third portions included in the first to third regions, respectively.
    Type: Application
    Filed: March 1, 2011
    Publication date: November 17, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shin HASHIMOTO, Katsushi AKITA, Yoshiyuki YAMAMOTO, Masaaki KUZUHARA, Norimasa YAFUNE
  • Publication number: 20110186861
    Abstract: A semiconductor device having a JFET or a MESFET mainly includes a semiconductor substrate, a first conductivity type semiconductor channel layer on the substrate, a first conductivity type semiconductor layer on the channel layer, and an i-type sidewall layer on a sidewall of a recess that penetrates the semiconductor layer to divide the semiconductor layer into a source region and a drain region. The semiconductor layer has an impurity concentration greater than an impurity concentration of the channel layer. The semiconductor device further includes a second conductivity type gate region that is located on the channel layer in the recess and on the i-type sidewall layer. The gate region is spaced from the source region and the drain region by the i-type sidewall layer.
    Type: Application
    Filed: January 26, 2011
    Publication date: August 4, 2011
    Applicant: DENSO CORPORATION
    Inventors: Rajesh Kumar MALHAN, Masaaki KUZUHARA
  • Patent number: 7973335
    Abstract: A field plate portion (5) overhanging a drain side in a visored shape is formed in a gate electrode (2). A multilayered film including a SiN film (21) and a SiO2 film (22) is formed beneath the field plate portion (5). The SiN film (21) is formed so that a surface of an AlGaN electron supply layer (13) is covered therewith.
    Type: Grant
    Filed: December 15, 2003
    Date of Patent: July 5, 2011
    Assignee: NEC Corporation
    Inventors: Yasuhiro Okamoto, Hironobu Miyamoto, Yuji Ando, Tatsuo Nakayama, Takashi Inoue, Masaaki Kuzuhara
  • Patent number: 7859014
    Abstract: The present invention provides a semiconductor device capable of suppressing current collapse, and also of preventing dielectric breakdown voltage and gain from lowering so as to perform high-voltage operation and realize an ideal high output. On a substrate (101), there are formed a buffer layer (102) made of a first GaN-based semiconductor, a carrier traveling layer (103) made of a second GaN-based semiconductor and a carrier supplying layer (104) made of a third GaN-based semiconductor. A recess structure (108) is made by eliminating a part of a first insulation film (107) and a part of the carrier supplying layer (104). Next, a gate insulation film (109) is deposited, and then a gate electrode (110) is formed so as to fill up the recess portion (108) and cover on over an area where the first insulation film (107) remains so that its portion on the drain electrode side is longer than that on the source electrode side.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: December 28, 2010
    Assignee: NEC Corporation
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yuji Ando, Masaaki Kuzuhara, Yasuhiro Okamoto, Takashi Inoue, Koji Hataya
  • Patent number: 7615868
    Abstract: There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 sequentially stacked in this order on the semiconductor film 101, characterized in that the first metal film 102 is formed of Al, and the second metal film 103 is formed of at least one metal selected from the group consisting of Nb, W, Fe, Hf, Re, Ta and Zr.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: November 10, 2009
    Assignee: NEC Corporation
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yuji Ando, Takashi Inoue, Yasuhiro Okamoto, Masaaki Kuzuhara
  • Patent number: 7459788
    Abstract: An ohmic electrode structure of a nitride semiconductor device having a nitride semiconductor. The ohmic electrode structure is provided with a first metal film formed on the nitride semiconductor and a second metal film formed on the first metal film. The first metal film is composed of at least one material selected from a group consisting of V, Mo, Ti, Nb, W, Fe, Hf, Re, Ta and Zr. The second metal film is composed of at least one material different from that of the first metal film (102), selected from a group consisting of V, Mo, Ti, Nb, W, Fe, Hf, Re, Ta, Zr, Pt and Au.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: December 2, 2008
    Assignee: NEC Corporation
    Inventors: Tatsuo Nakayama, Yuji Ando, Hironobu Miyamoto, Masaaki Kuzuhara, Yasuhiro Okamoto, Takashi Inoue, Koji Hataya
  • Publication number: 20080179743
    Abstract: There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 sequentially stacked in this order on the semiconductor film 101, characterized in that the first metal film 102 is formed of Al, and the second metal film 103 is formed of at least one metal selected from the group consisting of Nb, W, Fe, Hf, Re, Ta and Zr.
    Type: Application
    Filed: January 8, 2008
    Publication date: July 31, 2008
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yuji Ando, Takashi Inoue, Yasuhiro Okamoto, Masaaki Kuzuhara
  • Patent number: 7323783
    Abstract: There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 sequentially stacked in this order on the semiconductor film 101, characterized in that the first metal film 102 is formed of Al, and the second metal film 103 is formed of at least one metal selected from the group consisting of Nb, W, Fe, Hf, Re, Ta and Zr.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: January 29, 2008
    Assignee: NEC Corporation
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yuji Ando, Takashi Inoue, Yasuhiro Okamoto, Masaaki Kuzuhara
  • Publication number: 20080006853
    Abstract: The present invention provides a Schottky electrode for a nitride semiconductor device having a high barrier height, a low leak current performance and a low resistance and being thermally stable, and a process for production thereof. The Schottky electrode for a nitride semiconductor has a layered structure that comprises a copper (Cu) layer being in contact with the nitride semiconductor and a first electrode material layer formed on the copper (Cu) layer as an upper layer. As the first electrode material, a metal material which has a thermal expansion coefficient smaller than the thermal expansion coefficient of copper (Cu) and starts to undergo a solid phase reaction with copper (Cu) at a temperature of 400° C. or higher is employed.
    Type: Application
    Filed: July 8, 2005
    Publication date: January 10, 2008
    Applicant: NEC CORPORATION
    Inventors: Hironobu Miyamoto, Tatsuo Nakayama, Yuji Ando, Yasuhiro Okamoto, Masaaki Kuzuhara, Takashi Inoue, Koji Hataya
  • Patent number: 7256432
    Abstract: An electric-field control electrode (5) is formed between a gate electrode (2) and a drain electrode (3). A multilayered film including a SiN film (21) and a SiO2 film (22) is formed below the electric-field control electrode (5). The SiN film (21) is formed so that a surface of an AlGaN electron supply layer (13) is covered with the SiN film (21).
    Type: Grant
    Filed: December 15, 2003
    Date of Patent: August 14, 2007
    Assignee: NEC Corporation
    Inventors: Yasuhiro Okamoto, Hironobu Miyamoto, Yuji Ando, Tatsuo Nakayama, Takashi Inoue, Masaaki Kuzuhara
  • Publication number: 20070164305
    Abstract: An ohmic electrode structure of a nitride semiconductor device having a nitride semiconductor. The ohmic electrode structure is provided with a first metal film formed on the nitride semiconductor and a second metal film formed on the first metal film. The first metal film is composed of at least one material selected from a group consisting of V, Mo, Ti, Nb, W, Fe, Hf, Re, Ta and Zr. The second metal film is composed of at least one material different from that of the first metal film (102), selected from a group consisting of V, Mo, Ti, Nb, W, Fe, Hf, Re, Ta, Zr, Pt and Au.
    Type: Application
    Filed: February 28, 2005
    Publication date: July 19, 2007
    Inventors: Tatsuo Nakayama, Yuji Ando, Hironobu Miyamoto, Masaaki Kuzuhara, Yasuhiro Okamoto, Takashi Inoue, Koji Hataya
  • Publication number: 20070164326
    Abstract: A field effect transistor includes a semiconductor layer structure including GaN channel layer 12 and AlGa electron supply layer 13, source electrode 1 and drain electrode 3 which are formed on electron supply layer 13 so as to be separated from each other, gate electrode 2 formed between source electrode 1 and drain electrode 3, and SiON film 23 formed on electron supply layer 13. Gate electrode 2 has a field plate portion 5 that projects toward drain electrode 3 in the form of an eave on SiON film 23. The thickness of a portion (field plate layer 23a) of SiON film 23 lying between field plate portion 5 and electron supply layer 13 gradually increases from gate electrode 2 to drain electrode 3.
    Type: Application
    Filed: February 21, 2005
    Publication date: July 19, 2007
    Inventors: Yasuhiro Okamoto, Yuji Ando, Hironobu Miyamoto, Tatsuo Nakayama, Takashi Inque, Masaaki Kuzuhara
  • Publication number: 20070158692
    Abstract: The present invention provides a semiconductor device capable of suppressing current collapse, and also of preventing dielectric breakdown voltage and gain from lowering so as to perform high-voltage operation and realize an ideal high output. On a substrate (101), there are formed a buffer layer (102) made of a first GaN-based semiconductor, a carrier traveling layer (103) made of a second GaN-based semiconductor and a carrier supplying layer (104) made of a third GaN-based semiconductor. A recess structure (108) is made by eliminating a part of a first insulation film (107) and a part of the carrier supplying layer (104). Next, a gate insulation film (109) is deposited, and then a gate electrode (110) is formed so as to fill up the recess portion (108) and cover on over an area where the first insulation film (107) remains so that its portion on the drain electrode side is longer than that on the source electrode side.
    Type: Application
    Filed: June 24, 2005
    Publication date: July 12, 2007
    Applicant: NEC CORPORATION
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yuji Ando, Masaaki Kuzuhara, Yasuhiro Okamoto, Takashi Inoue, Koji Hataya
  • Publication number: 20070018316
    Abstract: There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 sequentially stacked in this order on the semiconductor film 101, characterized in that the first metal film 102 is formed of Al, and the second metal film 103 is formed of at least one metal selected from the group consisting of Nb, W, Fe, Hf, Re, Ta and Zr.
    Type: Application
    Filed: December 6, 2004
    Publication date: January 25, 2007
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yuji Ando, Takashi Inoue, Yasuhiro Okamoto, Masaaki Kuzuhara
  • Patent number: 7071526
    Abstract: A GaN semiconductor device with improved heat resistance of the Schottky junction electrode and excellent power performance and reliability is provided. In this semiconductor device having a Schottky gate electrode 17 which is in contact with an AlGaN electron supplying layer 14, a gate electrode 17 comprises a laminated structure wherein a first metal layer 171 formed of any of Ni, Pt and Pd, a second metal layer 172 formed of any of Mo, Pt, W, Ti, Ta, MoSi, PtSi, WSi, TiSi, TaSi, MoN, WN, TiN and TaN, and a third metal layer formed of any of Au, Cu, Al and Pt. Since the second metal layer comprises a metal material having a high melting point, it works as a barrier to the interdiffusion between the first metal layer and the third metal layer, and the deterioration of the gate characteristics caused by high temperature operation is suppressed.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: July 4, 2006
    Assignee: NEC Corporation
    Inventors: Yuji Ando, Hironobu Miyamoto, Yasuhiro Okamoto, Kensuke Kasahara, Tatsuo Nakayama, Masaaki Kuzuhara
  • Publication number: 20060054929
    Abstract: A semiconductor device includes, on a substrate (101), a buffer layer (102), and an channel layer (104), consisting essentially of semiconductor of a wultzite compound of group III-V, having a (0001) plane as a principal plane. The channel layer is subjected to compressive strain. A carrier supplying layer (103) is interposed between the channel layer (104) and the buffer layer (102). The carrier supplying layer (103) consists essentially of semiconductor of a wultzite compound of group III-V as a main component. N-type impurities are doped into the entire or part of the carrier supplying layer (103).
    Type: Application
    Filed: November 29, 2004
    Publication date: March 16, 2006
    Inventors: Tatsuo Nakayama, Yuji Ando, Hironobu Miyamoto, Kensuke Kasahara, Yasuhiro Okamoto, Masaaki Kuzuhara
  • Publication number: 20060043415
    Abstract: An electric-field control electrode (5) is formed between a gate electrode (2) and a drain electrode (3). A multilayered film including a SiN film (21) and a SiO2 film (22) is formed below the electric-field control electrode (5). The SiN film (21) is formed so that a surface of an AlGaN electron supply layer (13) is covered with the SiN film (21).
    Type: Application
    Filed: December 15, 2003
    Publication date: March 2, 2006
    Applicant: NEC Corporation
    Inventors: Yasuhiro Okamoto, Hironobu Miyamoto, Yuji Ando, Tatsuo Nakayama, Takashi Inoue, Masaaki Kuzuhara
  • Publication number: 20050151255
    Abstract: A GaN semiconductor device with improved heat resistance of the Schottky junction electrode and excellent power performance and reliability is provided. In this semiconductor device having a Schottky gate electrode 17 which is in contact with an AlGaN electron supplying layer 14, a gate electrode 17 comprises a laminated structure wherein a first metal layer 171 formed of any of Ni, Pt and Pd, a second metal layer 172 formed of any of Mo, Pt, W, Ti, Ta, MoSi, PtSi, WSi, TiSi, TaSi, MoN, WN, TiN and TaN, and a third metal layer formed of any of Au, Cu, Al and Pt. Since the second metal layer comprises a metal material having a high melting point, it works as a barrier to the interdiffusion between the first metal layer and the third metal layer, and the deterioration of the gate characteristics caused by high temperature operation is suppressed.
    Type: Application
    Filed: June 17, 2003
    Publication date: July 14, 2005
    Inventors: Yuji Ando, Hironobu Miyamoto, Yasuhiro Okamoto, Kensuke Kasahara, Tatsuo Nakayama, Masaaki Kuzuhara
  • Patent number: 6765241
    Abstract: A group III nitride semiconductor device of field effect transistor type having improved productivity, reduced parasitic capacitances adapted for excellent device performance in high-speed operation as well as good heat diffusion characteristics. The device includes an epitaxial growth layer of a group III nitride semiconductor with a buffer layer laid under it, formed on an A plane (an (11-20) plane) of a sapphire. Thereon a gate electrode, a source electrode, a drain electrode, and pad electrodes are formed, and a ground conductor layer is formed on the back face of the sapphire substrate. A thickness of said sapphire substrate tsub satisfies the following Equation (1).
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: July 20, 2004
    Assignee: NEC Corporation
    Inventors: Yasuo Ohno, Nobuyuki Hayama, Kensuke Kasahara, Tatsuo Nakayama, Hironobu Miyamoto, Yuji Takahashi, Yuji Ando, Kohji Matsunaga, Masaaki Kuzuhara