Patents by Inventor Masaaki Niwa

Masaaki Niwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7956413
    Abstract: In a method for manufacturing a semiconductor device having an N-channel field effect transistor, the N-channel field effect transistor is formed by a process including the steps of forming a high dielectric constant gate insulating film on a substrate, forming a gate electrode on the high dielectric constant gate insulating film, forming an extension region by introducing N-type impurities into the substrate by using at least the gate electrode as a mask, and forming a pocket region by introducing P-type impurities under the extension region in the substrate by using at least the gate electrode as a mask. An amount of arsenic (As) that is introduced as the N-type impurities is in a range that is equal to or lower than a prescribed value that is determined based on a thickness of the high dielectric constant gate insulating film.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: June 7, 2011
    Assignee: Panasonic Corporation
    Inventors: Yoshinao Harada, Shigenori Hayashi, Masaaki Niwa
  • Publication number: 20110100290
    Abstract: A meter system includes: an indicator including a pointer, a step motor, a stopper mechanism and a driving controller; and a flasher function unit including a flasher switch, a flasher and a flasher controller. The driving controller has: a stopper position detection operation executing element for executing a pointer moving away operation when a stopper position detection operation executing condition is satisfied and for executing a voltage detection type zero point stopper position detection operation when the executing condition is satisfied, and the flasher switch does not turn on and off, and a zero point return enforcement type zero point stopper position detection operation when the executing condition is satisfied, and the flasher switch turns on and off; a zero point setting element; and an applying element for applying the driving signal having the zero point.
    Type: Application
    Filed: October 27, 2010
    Publication date: May 5, 2011
    Applicant: DENSO CORPORATION
    Inventors: Hideyuki Nakane, Masaaki Niwa, Takashi Mizutani, Hironori Watarai, Teruyuki Anjima
  • Patent number: 7851297
    Abstract: A dual workfunction semiconductor device which comprises a first and second control electrode comprising a metal-semiconductor compound, e.g. a silicide or a germanide, and a dual workfunction semiconductor device thus obtained are disclosed. In one aspect, the method comprises forming a blocking region for preventing diffusion of metal from the metal-semiconductor compound of the first control electrode to the metal-semiconductor compound of the second control electrode, the blocking region being formed at a location where an interface between the first and second control electrodes is to be formed or is formed. By preventing metal to diffuse from the one to the other control electrode the constitution of the metal-semiconductor compounds of the first and second control electrodes may remain substantially unchanged during e.g. thermal steps in further processing of the device.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: December 14, 2010
    Assignee: IMEC
    Inventors: Stefan Jakschik, Jorge Adrian Kittl, Marcus Johannes Henricus van Dal, Anne Lauwers, Masaaki Niwa
  • Publication number: 20100208072
    Abstract: An on-vehicle display device 1 displays a video around a vehicle and travel information of the vehicle on a single display unit 20. The on-vehicle display device 1 includes video display enable/disable input units 11, 12, 13, and 14 inputting display enable/disable of the video around the vehicle, display modification units 30 and 40 modifying the display size of each of a video display section and a travel information display section on the basis of the input video display enable/disable, and an input prediction unit 30 predicting input of display enable/disable of the video around the vehicle. Even when video display disable is input from a video display enable/disable input unit, if the input prediction unit 30 predicts input of video display enable, the display modification units 30 and 40 do not modify the display size of each of the video display section and the travel information display section.
    Type: Application
    Filed: August 28, 2008
    Publication date: August 19, 2010
    Applicants: Toyota Jidosha Kabushiki Kaisha, Denso Corporation
    Inventors: Takahiko Murano, Kunihiko Toyofuku, Takeshi Tottori, Makoto Inomata, Masaaki Niwa, Naoyuki Aoki
  • Publication number: 20090242983
    Abstract: In a method for manufacturing a semiconductor device having an N-channel field effect transistor, the N-channel field effect transistor is formed by a process including the steps of forming a high dielectric constant gate insulating film on a substrate, forming a gate electrode on the high dielectric constant gate insulating film, forming an extension region by introducing N-type impurities into the substrate by using at least the gate electrode as a mask, and forming a pocket region by introducing P-type impurities under the extension region in the substrate by using at least the gate electrode as a mask. An amount of arsenic (As) that is introduced as the N-type impurities is in a range that is equal to or lower than a prescribed value that is determined based on a thickness of the high dielectric constant gate insulating film.
    Type: Application
    Filed: June 4, 2009
    Publication date: October 1, 2009
    Applicant: Panasonic Corporation
    Inventors: Yoshinao HARADA, Shigenori Hayashi, Masaaki Niwa
  • Patent number: 7554156
    Abstract: In a method for manufacturing a semiconductor device having an N-channel field effect transistor, the N-channel field effect transistor is formed by a process including the steps of forming a high dielectric constant gate insulating film on a substrate, forming a gate electrode on the high dielectric constant gate insulating film, forming an extension region by introducing N-type impurities into the substrate by using at least the gate electrode as a mask, and forming a pocket region by introducing P-type impurities under the extension region in the substrate by using at least the gate electrode as a mask. An amount of arsenic (As) that is introduced as the N-type impurities is in a range that is equal to or lower than a prescribed value that is determined based on a thickness of the high dielectric constant gate insulating film.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: June 30, 2009
    Assignee: Panasonic Corporation
    Inventors: Yoshinao Harada, Shigenori Hayashi, Masaaki Niwa
  • Publication number: 20090020821
    Abstract: A dual workfunction semiconductor device which comprises a first and second control electrode comprising a metal-semiconductor compound, e.g. a silicide or a germanide, and a dual workfunction semiconductor device thus obtained are disclosed. In one aspect, the method comprises forming a blocking region for preventing diffusion of metal from the metal-semiconductor compound of the first control electrode to the metal-semiconductor compound of the second control electrode, the blocking region being formed at a location where an interface between the first and second control electrodes is to be formed or is formed. By preventing metal to diffuse from the one to the other control electrode the constitution of the metal-semiconductor compounds of the first and second control electrodes may remain substantially unchanged during e.g. thermal steps in further processing of the device.
    Type: Application
    Filed: June 24, 2008
    Publication date: January 22, 2009
    Applicant: Interuniversitair Microelektronica Centrum vzw (IMEC)
    Inventors: Stefan Jakschik, Jorge Adrian Kittl, Marcus Johannes Henricus van Dal, Anne Lauwers, Masaaki Niwa
  • Publication number: 20060125006
    Abstract: In a method for manufacturing a semiconductor device having an N-channel field effect transistor, the N-channel field effect transistor is formed by a process including the steps of forming a high dielectric constant gate insulating film on a substrate, forming a gate electrode on the high dielectric constant gate insulating film, forming an extension region by introducing N-type impurities into the substrate by using at least the gate electrode as a mask, and forming a pocket region by introducing P-type impurities under the extension region in the substrate by using at least the gate electrode as a mask. An amount of arsenic (As) that is introduced as the N-type impurities is in a range that is equal to or lower than a prescribed value that is determined based on a thickness of the high dielectric constant gate insulating film.
    Type: Application
    Filed: October 21, 2005
    Publication date: June 15, 2006
    Inventors: Yoshinao Harada, Shigenori Hayashi, Masaaki Niwa
  • Patent number: 6955973
    Abstract: A metal film containing a metal is formed on a silicon layer, and then a surface portion of the silicon layer and the metal film are oxidized so as to form a silicon oxide film containing the metal in a surface portion of the silicon layer.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: October 18, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Masaaki Niwa
  • Patent number: 6812101
    Abstract: A zirconium silicate layer 103 is formed on a silicon substrate 100, a zirconium oxide layer 102 is also formed on the zirconium silicate layer 103, and the zirconium oxide layer 102 is then removed, thereby forming a gate insulating film 104 made of the zirconium silicate layer 103.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: November 2, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaru Moriwaki, Masaaki Niwa, Masafumi Kubota
  • Patent number: 6734451
    Abstract: On a silicon substrate is formed a silicon dioxide film and then hemispherical grains made of silicon, each having an extremely small diameter, are deposited thereon by LPCVD. After annealing the hemispherical grains, the silicon dioxide film is etched using the hemispherical grains as a first dotted mask, thereby forming a second dotted mask composed of the silicon dioxide film. The resulting second dotted mask is used to etch the silicon substrate to a specified depth from the surface thereof, thereby forming an aggregate of semiconductor micro-needles. Since the diameter of each of the semiconductor micro-needles is sufficiently small to cause the quantum size effects as well as has only small size variations, remarkable quantum size effects can be obtained. Therefore, it becomes possible to constitute a semiconductor apparatus with a high information-processing function by using the aggregate of semiconductor micro-needles (quantized region).
    Type: Grant
    Filed: October 22, 2002
    Date of Patent: May 11, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Eriguchi, Masafumi Kubota, Masaaki Niwa, Noboru Nomura
  • Publication number: 20030173586
    Abstract: A zirconium silicate layer 103 is formed on a silicon substrate 100, a zirconium oxide layer 102 is also formed on the zirconium silicate layer 103, and the zirconium oxide layer 102 is then removed, thereby forming a gate insulating film 104 made of the zirconium silicate layer 103.
    Type: Application
    Filed: January 10, 2003
    Publication date: September 18, 2003
    Inventors: Masaru Moriwaki, Masaaki Niwa, Masafumi Kubota
  • Publication number: 20030109114
    Abstract: A metal film containing a metal is formed on a silicon layer, and then a surface portion of the silicon layer and the metal film are oxidized so as to form a silicon oxide film containing the metal in a surface portion of the silicon layer.
    Type: Application
    Filed: December 9, 2002
    Publication date: June 12, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Masaaki Niwa
  • Patent number: 6559518
    Abstract: An MOS heterostructure includes: a single crystal silicon substrate; an insulating film formed on the substrate; and a conductive film formed on the insulating film. The substrate includes a plurality of terraces and steps, which have been formed as a result of rearrangement of silicon atoms on the surface of the substrate. Each of the step is located in a boundary between an adjacent pair of the terraces. The insulating film contains crystalline silicon dioxide that has grown epitaxially over the steps.
    Type: Grant
    Filed: September 22, 1999
    Date of Patent: May 6, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Masaaki Niwa
  • Publication number: 20030057451
    Abstract: On a silicon substrate is formed a silicon dioxide film and then hemispherical grains made of silicon, each having an extremely small diameter, are deposited thereon by LPCVD. After annealing the hemispherical grains, the silicon dioxide film is etched using the hemispherical grains as a first dotted mask, thereby forming a second dotted mask composed of the silicon dioxide film. The resulting second dotted mask is used to etch the silicon substrate to a specified depth from the surface thereof, thereby forming an aggregate of semiconductor micro-needles. Since the diameter of each of the semiconductor micro-needles is sufficiently small to cause the quantum size effects as well as has only small size variations, remarkable quantum size effects can be obtained. Therefore, it becomes possible to constitute a semiconductor apparatus with a high information-processing function by using the aggregate of semiconductor micro-needles (quantized region).
    Type: Application
    Filed: October 22, 2002
    Publication date: March 27, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Koji Eriguchi, Masafumi Kubota, Masaaki Niwa, Noboru Nomura
  • Patent number: 6489629
    Abstract: On a silicon substrate is formed a silicon dioxide film and then hemispherical grains made of silicon, each having an extremely small diameter, are deposited thereon by LPCVD. After annealing the hemispherical grains, the silicon dioxide film is etched using the hemispherical grains as a first dotted mask, thereby forming a second dotted mask composed of the silicon dioxide film. The resulting second dotted mask is used to etch the silicon substrate to a specified depth from the surface thereof, thereby forming an aggregate of semiconductor micro-needles. Since the diameter of each of the semiconductor micro-needles is sufficiently small to cause the quantum size effects as well as has only small size variations, remarkable quantum size effects can be obtained. Therefore, it becomes possible to constitute a semiconductor apparatus with a high information-processing function by using the aggregate of semiconductor micro-needles (quantized region).
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: December 3, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Eriguchi, Masafumi Kubota, Masaaki Niwa, Noboru Nomura
  • Patent number: 6273959
    Abstract: There is disclosed a semiconductor device cleaning method involving placing a cleaning solution containing 24 wt. % sulfuric acid, 5 wt. % hydrogen peroxide, 0.02 wt. % hydrogen fluoride, 0.075 wt. % n-dodecylbenzenesulfonic acid, and water into a quartz processing vessel and heating to no more than 100° C. A silicon wafer is immersed into the cleaning solution for 10 minutes and then washed by demineralized water for about 7 minutes. The surfaces of foreign particles on the wafer are etched by hydrogen fluoride, and n-dodecylbenzenesulfonic acid combines with the etched surfaces by sulfate ester bonding. The apparent diameter of the foreign particles increases and the repulsive force caused by zeta potential etc. increases, so that the foreign particles are unlikely to adhere to the surface of the silicon wafer permitting the foreign particles to be easily washed away in a water cleaning step.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: August 14, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Teruhito Oonishi, Ken Idota, Masaaki Niwa, Yoshinao Harada
  • Patent number: 6177291
    Abstract: On a silicon substrate is formed a silicon dioxide film and then hemispherical grains made of silicon. each having an extremely small diameter, are deposited thereon by LPCVD. After annealing the hemispherical grains, the silicon dioxide film is etched using the hemispherical grains as a first dotted mask, thereby forming a second dotted mask composed of the silicon dioxide film. The resulting second dotted mask is used to etch the silicon substrate to a specified depth from the surface thereof, thereby forming an aggregate of semiconductor micro-needles. Since the diameter of each of the semiconductor micro-needles is sufficiently small to cause the quantum size effects as well as has only small size variations, remarkable quantum size effects can be obtained. Therefore, it becomes possible to constitute a semiconductor apparatus with a high information-processing function by using the aggregate of semiconductor micro-needles (quantized region).
    Type: Grant
    Filed: February 8, 2000
    Date of Patent: January 23, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Eriguchi, Masafumi Kubota, Masaaki Niwa, Noboru Nomura
  • Patent number: 6087197
    Abstract: On a silicon substrate is formed a silicon dioxide film and then hemispherical grains made of silicon, each having an extremely small diameter, are deposited thereon by LPCVD. After annealing the hemispherical grains, the silicon dioxide film is etched using the hemispherical grains as a first dotted mask, thereby forming a second dotted mask composed of the silicon dioxide film. The resulting second dotted mask is used to etch the silicon substrate to a specified depth from the surface thereof, thereby forming an aggregate of semiconductor micro-needles. Since the diameter of each of the semiconductor micro-needles is sufficiently small to cause the quantum size effects as well as has only small size variations, remarkable quantum size effects can be obtained. Therefore, it becomes possible to constitute a semiconductor apparatus with a high information-processing function by using the aggregate of semiconductor micro-needles (quantized region).
    Type: Grant
    Filed: January 8, 1999
    Date of Patent: July 11, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Eriguchi, Masafumi Kubota, Masaaki Niwa, Noboru Nomura
  • Patent number: 6033928
    Abstract: On a silicon substrate is formed a silicon dioxide film and then hemispherical grains made of silicon, each having an extremely small diameter, are deposited thereon by LPCVD. After annealing the hemispherical grains, the silicon dioxide film is etched using the hemispherical grains as a first dotted mask, thereby forming a second dotted mask composed of the silicon dioxide film. The resulting second dotted mask is used to etch the silicon substrate to a specified depth from the surface thereof, thereby forming an aggregate of semiconductor micro-needles. Since the diameter of each of the semiconductor micro-needles is sufficiently small to cause the quantum size effects as well as has only small size variations, remarkable quantum size effects can be obtained. Therefore, it becomes possible to constitute a semiconductor apparatus with a high information-processing function by using the aggregate of semiconductor micro-needles (quantized region).
    Type: Grant
    Filed: November 2, 1994
    Date of Patent: March 7, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Eriguchi, Masafumi Kubota, Masaaki Niwa, Noboru Nomura