Patents by Inventor Masachika Masuda
Masachika Masuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7064011Abstract: A semiconductor device fabricating method comprises a substrate forming step of forming a plurality of separate conductive pads 20 on an adhesive layer included in an adhesive sheet 50, and a semiconductor chip mounting step of bonding semiconductor chips to the adhesive sheet 50 with surfaces thereof not provided with any electrodes in contact with the adhesive sheet 50, and electrically connecting electrodes 11 formed on the semiconductor chips 10 and upper parts of the conductive pads 20 with wires 30. The semiconductor chips 10, the wires 30 and the conductive pads 20 are sealed in a sealing resin molding 40, and then the adhesive sheet 50 is separated from the sealing resin molding 40. Each of the conductive pads 20 has a reduced part 20b, and a jutting part 20a jutting out from the reduced part 20b. The conductive pads 20 having such construction can be firmly bonded to the sealing resin molding 40.Type: GrantFiled: February 20, 2004Date of Patent: June 20, 2006Assignees: Dai Nippon Printing Co., Ltd., Nitto Denko CorporationInventors: Chikao Ikenaga, You Shimazaki, Masachika Masuda, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
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Patent number: 7061105Abstract: Two memory chips mounted over a base substrate have the same external size and a flash memory of the same memory capacity formed thereon. These memory chips are mounted over the base substrate with one of them being overlapped with the upper portion of the other one, and they are stacked with their faces being turned in the same direction. The bonding pads BP of one of the memory chips are disposed in the vicinity of the bonding pads BP of the other memory chip. In addition, the upper memory chip is stacked over the lower memory chip in such a way that the upper memory chip is slid in a direction (X direction) parallel to the one side of the lower memory chip and in a direction (Y direction) perpendicular thereto in order to prevent partial overlapping of it with the bonding pads BP of the lower memory chip.Type: GrantFiled: December 24, 2003Date of Patent: June 13, 2006Assignees: Hitachi, Ltd., Akita Electronics Systems Co., Ltd.Inventors: Masachika Masuda, Toshihiko Usami
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Patent number: 7053471Abstract: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner Accordingly, the small-sized memory card 1 can maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory card 1 can be used also in equipment which is designed to cope with the existing memory cards.Type: GrantFiled: October 10, 2002Date of Patent: May 30, 2006Assignees: Renesas Technologies Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Tamaki Wada, Hirotaka Nishizawa, Masachika Masuda, Kenji Osawa, Junichiro Osako, Satoshi Hatakeyama, Haruji Ishihara, Kazuo Yoshizaki, Kazunori Furusawa
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Patent number: 7012321Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.Type: GrantFiled: March 4, 2003Date of Patent: March 14, 2006Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano, Yasushi Takahashi, Masayasu Kawamura
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Publication number: 20060033191Abstract: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the small-sized memory card 1 can maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory card 1 can be used also in equipment which is designed to cope with the existing memory cards.Type: ApplicationFiled: August 16, 2005Publication date: February 16, 2006Inventors: Tamaki Wada, Hirotaka Nishizawa, Masachika Masuda, Kenji Osawa, Junichiro Osako, Satoshi Hatakeyama, Haruji Ishihara, Kazuo Yoshizaki, Kazunori Furusawa
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Publication number: 20050280131Abstract: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the small-sized memory card 1 can maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory card 1 can be used also in equipment which is designed to cope with the existing memory cards.Type: ApplicationFiled: August 16, 2005Publication date: December 22, 2005Inventors: Tamaki Wada, Hirotaka Nishizawa, Masachika Masuda, Kenji Osawa, Junichiro Osako, Satoshi Hatakeyama, Haruji Ishihara, Kazuo Yoshizaki, Kazunori Furusawa
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Publication number: 20050275071Abstract: A metal substrate apparatus comprises a plurality of metal substrates forming an IC card module used in manufacturing transfer mold-type non-contact IC cards. The metal substrate apparatus comprises a thin metal strip of processing material, and each metal substrate has connecting parts. Each metal substrate has a die pad for loading an IC chip. Antenna terminals to connect antenna coils are located outside the die pad and a resin-sealed region. The antenna terminals of one metal substrate and those of a longitudinally adjacent metal substrate overlap a shared region of the processing material in a width direction. The metal substrates can be separated by sealing and then making longitudinal cuts on the processing material on the outer parts of the metal substrates along two connecting lines.Type: ApplicationFiled: March 23, 2005Publication date: December 15, 2005Applicant: Dai Nippon Printing Co., Ltd.Inventors: Masachika Masuda, Chikao Ikenaga
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Publication number: 20050184380Abstract: A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.Type: ApplicationFiled: April 26, 2005Publication date: August 25, 2005Inventors: Kazuki Sakuma, Masayasu Kawamura, Yasushi Takahashi, Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano
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Patent number: 6924547Abstract: A memory card is disclosed which not only suppresses a lowering of the manufacturing yield caused by warping of a semiconductor chip sealing member, but also reduces the manufacturing cost by using a less expensive material. The memory card comprises a thin plate-like cap formed of a synthetic resin and a sealing member mounted inside the cap. Inside the sealing member are sealed a metallic lead frame and three semiconductor chips (two memory chips and one control chip) mounted on part (leads) of the lead frame. The semiconductor chips are electrically connected to leads through Au wires. Connecting terminals integral with the lead frame are exposed to the back side of the sealing member.Type: GrantFiled: May 23, 2003Date of Patent: August 2, 2005Assignee: Renesas Technology Corp.Inventors: Kouichi Kanemoto, Masachika Masuda
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Publication number: 20050093117Abstract: A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals.Type: ApplicationFiled: April 9, 2004Publication date: May 5, 2005Applicant: Dai Nippon Printing Co., Ltd.Inventors: Masachika Masuda, Chikao Ikenaga
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Publication number: 20050094433Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.Type: ApplicationFiled: December 3, 2004Publication date: May 5, 2005Inventors: Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano, Yasushi Takahashi, Masayasu Kawamura
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Patent number: 6885092Abstract: A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.Type: GrantFiled: December 2, 1999Date of Patent: April 26, 2005Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Kazuki Sakuma, Masayasu Kawamura, Yasushi Takahashi, Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano
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Patent number: 6858925Abstract: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the small-sized memory card 1 can maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory card 1 can be used also in equipment which is designed to cope with the existing memory cards.Type: GrantFiled: December 28, 2001Date of Patent: February 22, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Tamaki Wada, Hirotaka Nishizawa, Masachika Masuda, Kenji Osawa, Junichiro Osako, Satoshi Hatakeyama, Haruji Ishihara, Kazuo Yoshizaki, Kazunori Furusawa
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Patent number: 6853089Abstract: In the manufacture of a semiconductor device by adopting a block molding method wherein a semiconductor chip is fixed onto a wiring substrate through an adhesive, the occurrence of a defect caused by flowing-out of the adhesive is to be prevented. The semiconductor device according to the present invention comprises a wiring substrate, the wiring substrate having a main surface, an insulating film formed on the main surface, and electrodes formed on the main surface so as to be exposed from the insulating film, a semiconductor chip fixed through an adhesive onto the insulating film formed on the main surface of the wiring substrate, conductive wires for connecting the electrodes on the main surface of the wiring substrate and electrodes on the semiconductor chip with each other, and a seal member, i.e.Type: GrantFiled: August 22, 2002Date of Patent: February 8, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Mikako Ujiie, Michiaki Sugiyama, Kazunari Suzuki, Masachika Masuda, Tamaki Wada
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Publication number: 20050026323Abstract: For the manufacturing of semiconductor devices, in which multiple semiconductor chips which are mounted on a wiring substrate are processed for block molding and thereafter the wiring substrate is diced into individual resin-molded semiconductor devices, here is disclosed a technique for finding out easily, even after the dicing process, the position of each resin-molded semiconductor device in its former state on the wiring substrate. It includes processing steps of implementing the block molding with resin for multiple semiconductor chips mounted on a wiring substrate and thereafter dicing the wiring substrate into individual resin-molded semiconductor devices, with the substrate dicing step being preceded by a step of appending an address information pattern to each of the resin-molded semiconductor devices.Type: ApplicationFiled: August 25, 2004Publication date: February 3, 2005Inventors: Tsutomu Wada, Masachika Masuda
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Publication number: 20040197959Abstract: A method of manufacturing a semiconductor device, comprises providing a wiring substrate having a main surface, an insulating film formed on the main surface, and electrodes formed on the main surface so as to be exposed from the insulating film. A semiconductor chip is adhesively fixed to the insulating film. Conductive wires connect the electrodes on the main surface of the wiring substrate and electrodes on the chip. A groove is formed between the chip and the electrodes on the substrate. A protruding portion of the adhesive stays within the groove and does not reach the electrodes on the substrate.Type: ApplicationFiled: April 16, 2004Publication date: October 7, 2004Applicants: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Mikako Ujiie, Michiaki Sugiyama, Kazunari Suzuki, Masachika Masuda, Tamaki Wada
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Patent number: 6797539Abstract: For the manufacturing of semiconductor devices, in which multiple semiconductor chips which are mounted on a wiring substrate are processed for block molding and thereafter the wiring substrate is diced into individual resin-molded semiconductor devices, here is disclosed a technique for finding out easily, even after the dicing process, the position of each resin-molded semiconductor device in its former state on the wiring substrate. It includes processing steps of implementing the block molding with resin for multiple semiconductor chips mounted on a wiring substrate and thereafter dicing the wiring substrate into individual resin-molded semiconductor devices, with the substrate dicing step being preceded by a step of appending an address information pattern to each of the resin-molded semiconductor devices.Type: GrantFiled: May 16, 2003Date of Patent: September 28, 2004Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Tsutomu Wada, Masachika Masuda
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Publication number: 20040164387Abstract: A semiconductor device fabricating method comprises a substrate forming step of forming a plurality of separate conductive pads 20 on an adhesive layer included in an adhesive sheet 50, and a semiconductor chip mounting step of bonding semiconductor chips to the adhesive sheet 50 with surfaces thereof not provided with any electrodes in contact with the adhesive sheet 50, and electrically connecting electrodes 11 formed on the semiconductor chips 10 and upper parts of the conductive pads 20 with wires 30. The semiconductor chips 10, the wires 30 and the conductive pads 20 are sealed in a sealing resin molding 40, and then the adhesive sheet 50 is separated from the sealing resin molding 40. Each of the conductive pads 20 has a reduced part 20b, and a jutting part 20a jutting out from the reduced part 20b. The conductive pads 20 having such construction can be firmly bonded to the sealing resin molding 40.Type: ApplicationFiled: February 20, 2004Publication date: August 26, 2004Applicants: Dai Nippon Printing Co., Ltd., Nitto Denko CorporationInventors: Chikao Ikenaga, You Shimazaki, Masachika Masuda, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
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Publication number: 20040135262Abstract: Two memory chips mounted over a base substrate have the same external size and a flash memory of the same memory capacity formed thereon. These memory chips are mounted over the base substrate with one of them being overlapped with the upper portion of the other one, and they are stacked with their faces being turned in the same direction. The bonding pads BP of one of the memory chips are disposed in the vicinity of the bonding pads BP of the other memory chip. In addition, the upper memory chip is stacked over the lower memory chip in such a way that the upper memory chip is slid in a direction (X direction) parallel to the one side of the lower memory chip and in a direction (Y direction) perpendicular thereto in order to prevent partial overlapping of it with the bonding pads BP of the lower memory chip.Type: ApplicationFiled: December 24, 2003Publication date: July 15, 2004Inventors: Masachika Masuda, Toshihiko Usami
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Patent number: 6750080Abstract: Two semiconductor chips are bonded to each other with the rear surfaces of the respective semiconductor chips faced to each other, so that two longer sides of the semiconductor chips may confront the side of leads, and supporting leads are bonded and fixed onto the circuit forming surface of one of the semiconductor chips. The semiconductor chips are further bonded to each other in a state where the positions of the respective semiconductor chips are staggered relative to each other so that electrodes of one semiconductor chip may lie outside the other longer side of the other semiconductor chip, and that electrodes of the second semiconductor chip may lie outside the other longer side of the first semiconductor chip.Type: GrantFiled: February 25, 2003Date of Patent: June 15, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Tomoko Higashino, Takafumi Nishita, Hiroshi Ohno