Patents by Inventor Masaharu FURUYAMA

Masaharu FURUYAMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11317520
    Abstract: A circuit board includes: an insulating layer; a capacitor which is provided in the insulating layer and which includes a dielectric layer, a first conductor layer provided on a first surface of the dielectric layer and including an opening part, and a second conductor layer provided on a second surface opposite to the first surface of the dielectric layer and including a recess part at a position corresponding to the opening part; and a conductor via provided in the insulating layer, penetrating the dielectric layer, the opening part and the recess part, being in contact with the recess part, and being smaller than the opening part in plan view.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: April 26, 2022
    Assignee: FUJITSU INTERCONNECT TECHNOLOGIES LIMITED
    Inventors: Masaharu Furuyama, Daisuke Mizutani, Tomoyuki Akahoshi, Masateru Koide, Manabu Watanabe, Seigo Yamawaki, Kei Fukui
  • Patent number: 10896871
    Abstract: A circuit board includes an insulating layer; a capacitor which is provided in the insulating layer and includes a dielectric layer, a first conductor layer provided on a first surface of the dielectric layer and including a first opening part, and a second conductor layer provided on a second surface opposite to the first surface of the dielectric layer and including a second opening part at a position corresponding to the first opening part; a first conductor via provided in the insulating layer, penetrating the dielectric layer, the first opening part and the second opening part, and being smaller than the first opening part and the second opening part in plan view; a second conductor via provided in the insulating layer and making contact with the second conductor layer; and a third conductor layer provided on the insulating layer and electrically coupled to the first and the second conductor vias.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: January 19, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Tomoyuki Akahoshi, Masaharu Furuyama, Daisuke Mizutani
  • Publication number: 20190306981
    Abstract: A circuit substrate includes a first insulating layer, a capacitor disposed over the first insulating layer, the capacitor including a dielectric layer, a first conductor layer disposed on a first face of the dielectric layer, and a second conductor layer disposed on a second face opposite to the first face of the dielectric layer and having an electric resistivity higher than that of the first conductor layer, a third conductor layer disposed on a surface of the second conductor layer, the third conductor layer having an electric resistivity lower than that of the second conductor layer, a second insulating layer covering the capacitor, and a conductor via disposed in the second insulating layer, the conductor via being coupled to a portion of the third conductor layer.
    Type: Application
    Filed: January 31, 2019
    Publication date: October 3, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Masaharu Furuyama, Daisuke Mizutani, Tomoyuki AKAHOSHI
  • Publication number: 20190053385
    Abstract: A circuit board includes: an insulating layer; a capacitor which is provided in the insulating layer and which includes a dielectric layer, a first conductor layer provided on a first surface of the dielectric layer and including an opening part, and a second conductor layer provided on a second surface opposite to the first surface of the dielectric layer and including a recess part at a position corresponding to the opening part; and a conductor via provided in the insulating layer, penetrating the dielectric layer, the opening part and the recess part, being in contact with the recess part, and being smaller than the opening part in plan view.
    Type: Application
    Filed: October 17, 2018
    Publication date: February 14, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Masaharu Furuyama, Daisuke Mizutani, Tomoyuki AKAHOSHI, Masateru Koide, MANABU WATANABE, Seigo Yamawaki, Kei FUKUI
  • Publication number: 20190051598
    Abstract: A circuit board includes an insulating layer, a capacitor which is provided in the insulating layer and includes a dielectric layer, a first conductor layer provided on a first surface of the dielectric layer and including a first opening part, and a second conductor layer provided on a second surface opposite to the first surface of the dielectric layer and including a second opening part at a position corresponding to the first opening part; a first conductor via provided in the insulating layer, penetrating the dielectric layer, the first opening part and the second opening part, and being smaller than the first opening part and the second opening part in plan view; a second conductor via provided in the insulating layer and making contact with the second conductor layer; and a third conductor layer provided on the insulating layer and electrically coupled to the first and the second conductor vias.
    Type: Application
    Filed: October 18, 2018
    Publication date: February 14, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Tomoyuki AKAHOSHI, Masaharu Furuyama, Daisuke Mizutani
  • Patent number: 8952271
    Abstract: There is provided a circuit board to which a solder ball composed of a lead (Pb)-free solder is to be connected, a semiconductor device including an electrode and a solder ball composed of a lead (Pb)-free solder disposed on the electrode, and a method of manufacturing the semiconductor device, in which mounting reliability can be improved by enhancing the bonding strength (adhesion strength) between the solder ball composed of a lead (Pb)-free solder and the electrode.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: February 10, 2015
    Assignee: Fujitsu Limited
    Inventors: Masaharu Furuyama, Daisuke Mizutani, Seiki Sakuyama, Toshiya Akamatsu
  • Publication number: 20140103097
    Abstract: There is provided a circuit board to which a solder ball composed of a lead (Pb)-free solder is to be connected, a semiconductor device including an electrode and a solder ball composed of a lead (Pb)-free solder disposed on the electrode, and a method of manufacturing the semiconductor device, in which mounting reliability can be improved by enhancing the bonding strength (adhesion strength) between the solder ball composed of a lead (Pb)-free solder and the electrode.
    Type: Application
    Filed: December 13, 2013
    Publication date: April 17, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Masaharu Furuyama, Daisuke Mizutani, Seiki Sakuyama, Toshiya Akamatsu
  • Publication number: 20090090543
    Abstract: There is provided a circuit board to which a solder ball composed of a lead (Pb)-free solder is to be connected, a semiconductor device including an electrode and a solder ball composed of a lead (Pb)-free solder disposed on the electrode, and a method of manufacturing the semiconductor device, in which mounting reliability can be improved by enhancing the bonding strength (adhesion strength) between the solder ball composed of a lead (Pb)-free solder and the electrode.
    Type: Application
    Filed: October 1, 2008
    Publication date: April 9, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Masaharu FURUYAMA, Daisuke MIZUTANI, Seiki SAKUYAMA, Toshiya AKAMATSU