Patents by Inventor Masaharu Wada

Masaharu Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240282359
    Abstract: A memory includes a cell array including first and second sub arrays including memory cells and simultaneously driven in a read or a write operation. First lines are connected to the cells corresponding to one of physical rows, where the physical row is the cells arranged in a first direction in the cell array. Second lines are connected to the cells arranged in a second direction intersecting with the first direction in the cell array. A decoder selects a selection line from among the first lines in accordance with a logical row address corresponding to each of the physical rows and applies a read voltage or a write voltage to the selection line. A sense amplifier detects data from the second lines. Logical row addresses corresponding to physical rows adjacent to a certain physical row among the physical rows differ between the first sub array and the second sub array.
    Type: Application
    Filed: February 20, 2024
    Publication date: August 22, 2024
    Applicant: Kioxia Corporation
    Inventors: Takeshi AOKI, Masaharu WADA, Takayuki MIYAZAKI, Takashi INUKAI
  • Patent number: 11996138
    Abstract: A first transistor is coupled to a capacitor. A first inverter circuit is coupled between first and second nodes, and includes a p-type second transistor and an n-type third transistor coupled at a third node. A second inverter circuit is coupled between the first and second nodes, and includes a p-type fourth transistor and an n-type fifth transistor coupled at a fourth node. A sixth transistor is coupled between gates of the fourth and fifth transistors, and the third node. A seventh transistor is coupled between gates of the second and third transistors, and the fourth node. An eighth transistor is coupled between the gate of the second transistor and the third node. A ninth transistor is coupled between the gate of the fourth transistor and the fourth node.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: May 28, 2024
    Assignee: Kioxia Corporation
    Inventor: Masaharu Wada
  • Publication number: 20240057314
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate and a capacitor that includes a first electrode extending in a first direction intersecting the semiconductor substrate and a second electrode facing the first electrode. A first conductive layer is above the capacitor and extends in a second direction. A semiconductor layer penetrates the first conductive layer in the first direction. A first conductor can be above or below the first conductive layer and electrically connected to the first conductive layer. A first insulating film is between the first conductive layer and the semiconductor layer. A second conductive layer extends in the second direction and is electrically connected to the first conductive layer via the first conductor.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 15, 2024
    Inventors: Takeshi AOKI, Takayuki MIYAZAKI, Masaharu WADA, Takashi INUKAI
  • Publication number: 20230402088
    Abstract: A first inverter includes second and third transistors coupled at a third node. A second inverter includes fourth and fifth transistors coupled at a fourth node. A sixth transistor is between the fifth transistor's gate and the third node. A seventh transistor is between the third transistor's gate and the fourth node. An eighth transistor is between the third transistor's gate and the third node. A ninth transistor is between the fifth transistor's gate and the fourth node. A voltage of the eighth and ninth transistors' gates lowers at a first time. A state is formed with voltages applied to first and second nodes of the first and second inverters at a second time. A voltage of the sixth and seventh transistors' gates rises between the first and second times.
    Type: Application
    Filed: December 5, 2022
    Publication date: December 14, 2023
    Applicant: Kioxia Corporation
    Inventor: Masaharu Wada
  • Patent number: 11776616
    Abstract: A semiconductor memory device includes a memory cell that includes a capacitor including a first and second end and a first transistor. The first transistor includes a third and fourth end, is coupled to the first end at the fourth end, and contains an oxide semiconductor. A bit line is coupled to the third end. A sense amplifier is coupled to the bit line and coupled between a first node of a first potential and a second node of a second potential lower than the first potential. A potential generator is configured to supply the second end with a fourth potential that is different from a third potential intermediate between the first potential and the second potential.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: October 3, 2023
    Assignee: Kioxia Corporation
    Inventor: Masaharu Wada
  • Publication number: 20230197141
    Abstract: A first transistor is coupled to a capacitor. A first inverter circuit is coupled between first and second nodes, and includes a p-type second transistor and an n-type third transistor coupled at a third node. A second inverter circuit is coupled between the first and second nodes, and includes a p-type fourth transistor and an n-type fifth transistor coupled at a fourth node. A sixth transistor is coupled between gates of the fourth and fifth transistors, and the third node. A seventh transistor is coupled between gates of the second and third transistors, and the fourth node. An eighth transistor is coupled between the gate of the second transistor and the third node. A ninth transistor is coupled between the gate of the fourth transistor and the fourth node.
    Type: Application
    Filed: June 7, 2022
    Publication date: June 22, 2023
    Applicant: Kioxia Corporation
    Inventor: Masaharu WADA
  • Publication number: 20230200051
    Abstract: A semiconductor memory device comprises a memory cell array. The memory cell array comprises sub arrays. The sub array comprises: memory portions; first semiconductor layers electrically connected to memory portions; first gate electrodes respectively facing first semiconductor layers; a first wiring electrically connected to first semiconductor layers; second wirings connected to first gate electrodes; second semiconductor layers electrically connected to first end portions of second wirings; second gate electrodes facing second semiconductor layers; and a third wiring electrically connected to second semiconductor layers. The memory cell array comprises fourth wirings that extend in one direction across the sub arrays and are connected to second gate electrodes.
    Type: Application
    Filed: June 15, 2022
    Publication date: June 22, 2023
    Applicant: Kioxia Corporation
    Inventors: Takeshi AOKI, Masaharu WADA, Mamoru ISHIZAKA, Tsuneo INABA
  • Patent number: 11665882
    Abstract: A semiconductor memory device, includes: a first region including a first memory cell array; a second region arranged with the first region; and a third region arranged with the second region and including a second memory cell array. Each memory cell array includes: a field effect transistor above a semiconductor substrate, including a gate, a source, and a drain, the gate being connected to a first wiring, and one of the source and the drain being connected to a second wiring; and a capacitor below the transistor, including a first electrode connected to the other of the source and the drain, a second electrode facing the first electrode, and a third electrode connected to the second electrode and extending to the second region. The second region includes a conductor, the conductor connecting the third electrodes of the memory cell arrays.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: May 30, 2023
    Assignee: Kioxia Corporation
    Inventors: Masaharu Wada, Mutsumi Okajima, Tsuneo Inaba, Shinji Miyano
  • Publication number: 20220406783
    Abstract: A semiconductor memory device includes a substrate, memory layers, a first wiring disposed at a position closer to the substrate than memory layers or a position farther from the substrate than memory layers, a transistor layer disposed between memory layers and the first wiring, and a second wiring connected to the memory layers and the transistor layer. Each of memory layers includes a memory unit, a first semiconductor layer connected between the memory unit and the second wiring, a first electrode opposed to the first semiconductor layer, a third wiring connected to the first electrode, a second semiconductor layer electrically connected to one end portion of the third wiring, and a second electrode opposed to the second semiconductor layer. The transistor layer includes a third semiconductor layer connected between the first wiring and the second wiring, and a third electrode opposed to the third semiconductor layer.
    Type: Application
    Filed: December 10, 2021
    Publication date: December 22, 2022
    Applicant: Kioxia Corporation
    Inventors: Masaharu WADA, Mutsumi OKAJIMA
  • Patent number: 11462542
    Abstract: According to one embodiment, a semiconductor storage device includes a plurality of first wires extending in a first direction, a plurality of second wires extending in a second direction intersecting the first direction, and a plurality of first semiconductor transistors. Each first semiconductor transistor is respectively connected between one of the plurality of first wires and one of the plurality of second wires. Each first semiconductor transistor includes a gate electrode connected to the respective first wire and a channel layer on a first surface of the second wire and also a side surface of the respective second wire.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: October 4, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Masaharu Wada, Keiji Ikeda
  • Publication number: 20220310153
    Abstract: A semiconductor memory device includes a memory cell that includes a capacitor including a first and second end and a first transistor. The first transistor includes a third and fourth end, is coupled to the first end at the fourth end, and contains an oxide semiconductor. A bit line is coupled to the third end. A sense amplifier is coupled to the bit line and coupled between a first node of a first potential and a second node of a second potential lower than the first potential. A potential generator is configured to supply the second end with a fourth potential that is different from a third potential intermediate between the first potential and the second potential.
    Type: Application
    Filed: September 10, 2021
    Publication date: September 29, 2022
    Applicant: Kioxia Corporation
    Inventor: Masaharu WADA
  • Patent number: 11238919
    Abstract: According to one embodiment, a semiconductor storage device includes a first stacked portion including a first peripheral circuit and a second stacked portion above the first stacked portion. The second stacked portion including a memory cell, a word line connected to the memory cell, a bit line connected to the memory cell and the first peripheral circuit, and at least one of a second peripheral circuit connected to the bit line and a third peripheral circuit connected to the word line. The at least one of the second or third peripheral circuits including a field effect transistor having a channel layer containing an oxide semiconductor.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: February 1, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Masaharu Wada
  • Publication number: 20210225847
    Abstract: A semiconductor memory device, includes: a first region including a first memory cell array; a second region arranged with the first region; and a third region arranged with the second region and including a second memory cell array. Each memory cell array includes: a field effect transistor above a semiconductor substrate, including a gate, a source, and a drain, the gate being connected to a first wiring, and one of the source and the drain being connected to a second wiring; and a capacitor below the transistor, including a first electrode connected to the other of the source and the drain, a second, electrode facing the first electrode, and a third electrode connected to the second electrode and extending to the second region. The second region includes a conductor, the conductor connecting the third electrodes of the memory cell arrays.
    Type: Application
    Filed: September 4, 2020
    Publication date: July 22, 2021
    Applicant: Kioxia Corporation
    Inventors: Masaharu WADA, Mutsumi OKAJIMA, Tsuneo INABA, Shinji MIYANO
  • Publication number: 20210201980
    Abstract: According to one embodiment, a semiconductor storage device includes a first stacked portion including a first peripheral circuit and a second stacked portion above the first stacked portion. The second stacked portion including a memory cell, a word line connected to the memory cell, a bit line connected to the memory cell and the first peripheral circuit, and at least one of a second peripheral circuit connected to the bit line and a third peripheral circuit connected to the word line. The at least one of the second or third peripheral circuits including a field effect transistor having a channel layer containing an oxide semiconductor.
    Type: Application
    Filed: August 28, 2020
    Publication date: July 1, 2021
    Inventor: Masaharu WADA
  • Publication number: 20210082921
    Abstract: According to one embodiment, a semiconductor storage device includes a plurality of first wires extending in a first direction, a plurality of second wires extending in a second direction intersecting the first direction, and a plurality of first semiconductor transistors. Each first semiconductor transistor is respectively connected between one of the plurality of first wires and one of the plurality of second wires. Each first semiconductor transistor includes a gate electrode connected to the respective first wire and a channel layer on a first surface of the second wire and also a side surface of the respective second wire.
    Type: Application
    Filed: February 27, 2020
    Publication date: March 18, 2021
    Inventors: Masaharu WADA, Keiji IKEDA
  • Patent number: 10734448
    Abstract: A semiconductor integrated circuit includes a cell array, an input unit and an output unit. Cell array includes word lines, bit lines and resistance change cells respectively formed at cross points between word lines and bit lines. Input unit includes an access controller and a driver. Access controller controls access of data to a cell in time series, the data being expressed by a matrix. Driver applies voltage to a word line coupled to the cell which is an access destination of the data, the voltage being adjusted depending on a value of the data to be accessed to the cell. The output unit includes holding circuits each holding a representative value of an output level of a corresponding one of the bit lines in time series.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: August 4, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Masaharu Wada
  • Publication number: 20200075677
    Abstract: According to one embodiment, a semiconductor integrated circuit includes a cell array, an input unit and an output unit. Cell array includes word lines, bit lines and resistance change cells respectively formed at cross points between word lines and bit lines. Input unit includes an access controller and a driver. Access controller controls access of data to a cell in time series, the data being expressed by a matrix. Driver applies voltage to a word line coupled to the cell which is an access destination of the data, the voltage being adjusted depending on a value of the data to be accessed to the cell. The output unit includes holding circuits each holding a representative value of an output level of a corresponding one of the bit lines in time series.
    Type: Application
    Filed: February 21, 2019
    Publication date: March 5, 2020
    Applicant: Toshiba Memory Corporation
    Inventor: Masaharu WADA
  • Patent number: 9707663
    Abstract: A polishing pad is provided with a compression elastic modulus of 0.17 MPa or more and 0.32 MPa or less produced by preparing a nonwoven fabric formed of bundles of ultrafine fibers with an average monofilament diameter of 3.0 ?m or more and 8.0 ?m or less, preparing a polishing pad base by impregnating the nonwoven fabric with a polyurethane based elastomer in an amount of 20 mass % or more and 50 mass % or less relative to the mass of the polishing pad base, and laminating the polishing pad base with a porous polyurethane layer containing wet-solidified polyurethane as primary component which has openings with an average opening diameter of 10 ?m or more and 90 ?m or less in its surface to serve as polishing surface layer.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: July 18, 2017
    Assignees: Toray Industries, Inc., Toray Coatex Co., Ltd.
    Inventors: Kuniyasu Shiro, Masaharu Wada, Hiroyasu Kato, Hajime Nishimura, Satoshi Yanagisawa, Yukihiro Matsuzaki
  • Patent number: 8837240
    Abstract: A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data storage circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data storage circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Iwai, Makoto Takahashi, Masaharu Wada, Mariko Iizuka, Kimimasa Imai
  • Patent number: 8791750
    Abstract: A constant voltage constant current generation circuit includes a first transistor, a first resistor connected between the first terminal and a second potential, a first diode connected in series with the first resistor, and a first operational amplifier which outputs a first control signal to a control terminal of the first transistor. The constant voltage constant current generation circuit includes a current output circuit which outputs a constant current from a current output terminal according to the first control signal, a second transistor through which a second current flows, the second current obtained by mirroring a first current flowing through the first transistor, a second resistor connected between the voltage output terminal and the second potential.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: July 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masaharu Wada