Patents by Inventor Masaharu Yamaji

Masaharu Yamaji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180130868
    Abstract: Warping of a semiconductor wafer occurring due to a difference in the thermal expansion rates of an insulating film and the semiconductor wafer is restricted. Therefore, processing failures and conveying failures in the manufacturing process, as well as cracking of the semiconductor wafer, are restricted. Provided is a high breakdown voltage passive element including a substrate, a lower metal layer and upper metal layer stacked on the substrate, and an insulating unit formed between the lower metal layer and upper metal layer, wherein the insulating unit has a first insulating film whose thermal expansion rate is lower than the thermal expansion rate of the substrate, and a second insulating film, formed on the first insulating film, whose thermal expansion rate is higher than the thermal expansion rate of the substrate.
    Type: Application
    Filed: January 8, 2018
    Publication date: May 10, 2018
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu YAMAJI
  • Publication number: 20180069076
    Abstract: An HVJT is includes a parasitic diode formed by pn junction between an n?-type diffusion region and a second p?-type separation region surrounding a periphery thereof. The n?-type diffusion region is arranged between an n-type diffusion region that is a high potential side region and an n-type diffusion region that is a low potential side region, and electrically separates these regions. In the n?-type diffusion region, an nchMOSFET of a level-up level shift circuit is arranged. The n?-type diffusion region has a planar layout in which the n?-type diffusion region surrounds a periphery of the n-type diffusion region and a region where the nchMOSFET is arranged protrudes inwardly. A high-concentration inter-region distance L1 of the nchMOS region where the nchMOSFET is arranged is longer than a high-concentration inter-region distance L2 of the parasitic diode. Thus, the reliability of the semiconductor device may be improved.
    Type: Application
    Filed: October 31, 2017
    Publication date: March 8, 2018
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide TANAKA, Masaharu YAMAJI
  • Publication number: 20180061827
    Abstract: A semiconductor integrated circuit includes a semiconductor substrate of a first conductivity type, a first well region of a second conductivity type formed in an upper portion of the semiconductor substrate, a second well region of the first conductivity type formed in an upper portion of the first well region, an insulating layer formed separated from the first well region on a bottom portion of the semiconductor substrate that is directly beneath the first well region, and a rear surface electrode layer formed on a bottom of the insulating layer.
    Type: Application
    Filed: July 5, 2017
    Publication date: March 1, 2018
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Hiroshi KANNO, Masaharu YAMAJI, Akihiro JONISHI
  • Publication number: 20170365598
    Abstract: An HVIC is a gate driver IC that drives a three-phase inverter and includes high-potential-side regions for three phases on a single semiconductor substrate. The high-potential-side region includes an n-type region and has a potential that is fixed at a power source voltage potential through a VB contact region in the n-type region. The high-potential-side region has a high-side driving circuit that drives an upper arm element of the inverter. An interphase region between adjacent high-potential-side regions has no GND contact region and no GND contact electrode arranged therein, and has only a p-type region at a ground potential constituting a low-potential-side region. The high-potential-side region of one phase has a p?-type opening between the high-side driving circuit of thereof and the high-side driving circuit or the GND contact region of an adjacent high-potential-side region that is of another phase and sandwiches the interphase region therebetween.
    Type: Application
    Filed: April 28, 2017
    Publication date: December 21, 2017
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu YAMAJI
  • Patent number: 9773878
    Abstract: A semiconductor device includes a first main electrode terminal and second main electrode terminal disposed on the principal surface of a semiconductor substrate so as to be spaced from one another, an insulating film formed on the principal surface of the semiconductor substrate, and a thin film resistance layer. One end side of the thin film resistance layer is connected to the first main electrode terminal and the other end side of the thin film resistance layer is connected to the second main electrode terminal, the thin film resistance layer being spirally formed on the insulating film in such a way as to surround the first main electrode terminal. The thin film resistance layer extends while oscillating in a thickness direction of the semiconductor substrate.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: September 26, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide Tanaka, Masaharu Yamaji
  • Publication number: 20170271506
    Abstract: An nchMOSFET of a level-raising circuit is arranged in a high voltage junction termination region (HVJT), to be integrated with a parasitic diode formed by an n?-type diffusion region and a second p-type separation region. On a high potential side of the HVJT, a first field plate (FP) also acting as a drain electrode of the nchMOSFET and a second FP also acting as a cathode electrode of a parasitic diode are arranged away from each other. On a low potential side the HVJT, a third electrode also acting as a source electrode of the nchMOSFET is arranged in a planar layout surrounding the periphery of a high potential side region. On an interlayer insulating film, an interval between a first portion of the third FP and a fourth portion of the first FP is larger than an interval between the second and the third FPs.
    Type: Application
    Filed: March 7, 2017
    Publication date: September 21, 2017
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu YAMAJI
  • Patent number: 9762048
    Abstract: A first sense resistor is connected between a fourth terminal of a power source potential of a high-potential region and a first terminal of a ground potential. A second sense resistor is connected between a third terminal of a reference potential of the high-potential region and the first terminal. A comparator is disposed in a low-potential region and uses the ground potential as a reference potential for operation. The comparator compares a voltage between an intermediate potential point of the first sense resistor and an intermediate potential point of the second sense resistor with a predetermined reference voltage. The output of the comparator is input through a control circuit and a level shift circuit to a high-side drive circuit driving an upper-arm IGBT. The output of the comparator is input to a driver circuit driving a lower-arm IGBT.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: September 12, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide Tanaka, Masaharu Yamaji
  • Patent number: 9722019
    Abstract: A high voltage integrated circuit device suppresses the quantity of holes that are implanted due to a negative voltage surge, thus preventing malfunction and destruction of a high side circuit. A p?-type aperture portion has a gap portion in an n-type well region that is a voltage resistant region, penetrating the n-type well region to reach a p-type substrate, so as to enclose an n-type well region that is a high potential region.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: August 1, 2017
    Assignee: FUJI ELECTRIC CO., LTD
    Inventor: Masaharu Yamaji
  • Publication number: 20170207296
    Abstract: An interlayer insulating film is disposed on a LOCOS oxide film covering an n-type drift region of a JFET. A polysilicon resistor having a spiral planar shape is disposed in the interlayer insulating film. A spiral wire in an outermost circumference of the polysilicon resistor is covered by a source electrode wire that extends on the interlayer insulating film. An end of the polysilicon resistor is electrically connected to a drain electrode wire. A ground terminal wire and a voltage division terminal wire are electrically connected to a spiral wire farther on an inner circumference side by one or more wires than the spiral wire. A portion farther on an inner circumference side than the spiral wire is used as a resistive element, and voltage for an input pad of the JFET is thereby divided to be taken out as a potential of the voltage division terminal wire.
    Type: Application
    Filed: November 30, 2016
    Publication date: July 20, 2017
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Taichi KARINO, Masaharu YAMAJI
  • Patent number: 9711659
    Abstract: A semiconductor device includes a first conductive type first main electrode region, a first conductive type drift region which makes contact with the first main electrode region, a first conductive type second main electrode region which makes contact with the drift region, a second conductive type well region which is provided in a part of a surface layer portion of the drift region and to which a reference potential is applied, and a first conductive type potential extracting region which is provided in a surface layer portion of the well region and to which the reference potential is applied. The well region serves as a base region which controls a current flowing between the potential extracting region and the drift region. Thus, it is possible to provide a novel semiconductor device which is high in reliability while the increase of the chip size can be suppressed.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: July 18, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Taichi Karino, Masaru Saito, Masaharu Yamaji, Osamu Sasaki
  • Publication number: 20170170647
    Abstract: A first sense resistor is connected between a fourth terminal of a power source potential of a high-potential region and a first terminal of a ground potential. A second sense resistor is connected between a third terminal of a reference potential of the high-potential region and the first terminal. A comparator is disposed in a low-potential region and uses the ground potential as a reference potential for operation. The comparator compares a voltage between an intermediate potential point of the first sense resistor and an intermediate potential point of the second sense resistor with a predetermined reference voltage. The output of the comparator is input through a control circuit and a level shift circuit to a high-side drive circuit driving an upper-arm IGBT. The output of the comparator is input to a driver circuit driving a lower-arm IGBT.
    Type: Application
    Filed: November 1, 2016
    Publication date: June 15, 2017
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide TANAKA, Masaharu YAMAJI
  • Publication number: 20170170285
    Abstract: A resistive field plate including a spiral resistive element and meander resistive element is provided in an edge termination structure portion. The spiral resistive element is formed in a spiral planar layout, surrounding the periphery of a high-potential-side region to span from the high-potential-side region to a low-potential-side region. A spiral wire of the spiral resistive element includes a conductive film layer and a thin-film resistive layer connected to each other. The meander resistive element has ends positioned in the high-potential-side region and the low-potential-side region, and is provided in a meandering planar layout. The meander resistive element is provided at a same level as that of the thin-film resistive layer, and faces in the depth direction the conductive film layer of the spiral resistive element, sandwiching an interlayer insulating film therebetween. The conductive film layer of the spiral resistive element and the meander resistive element constitute a field plate.
    Type: Application
    Filed: December 12, 2016
    Publication date: June 15, 2017
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide TANAKA, Masaharu YAMAJI
  • Publication number: 20170133401
    Abstract: A semiconductor integrated circuit includes a semiconductor layer of a first conductivity type which is stacked on a support substrate with an insulating layer interposed between the semiconductor layer and the supp ort substrate, a first well region of a second conductivity type buried in an upper part of the semiconductor layer so as to be separated from the insulating layer, a second well region of the first conductivity type buried in an upper part of the first well region, and an isolation region of the first conductivity type buried in the upper part of the semiconductor layer such that the isolation region surrounds the first well region and is separated from the first well region and the insulating layer.
    Type: Application
    Filed: January 25, 2017
    Publication date: May 11, 2017
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroshi KANNO, Hitoshi SUMIDA, Masaharu YAMAJI
  • Patent number: 9608072
    Abstract: A semiconductor device is provided with a first well region of a first conduction type having a first voltage (voltage VB) applied thereto, a second well region of a second conduction type formed in the surface layer section of the first well region and having a second voltage (voltage VS) different from the first voltage applied thereto, and a charge extracting region of the first conduction type formed in the surface layer section of the second well region and having the first voltage applied thereto. This inhibits the operation of a parasitic bipolar transistor.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: March 28, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroshi Kanno, Hitoshi Sumida, Masaharu Yamaji
  • Patent number: 9537486
    Abstract: In a semiconductor device such as a three-phase one-chip gate driver IC, HVNMOSs configuring two set and reset level shift circuits are disposed on non-opposed surfaces, and it is thereby possible to reduce the amount of electrons flowing into drains of HVNMOSs of another phase due to a negative voltage surge. Also, distances from an opposed surface on the opposite side to the respective drains of the HVNMOSs configuring the two set and reset level shift circuits are made equal to or more than 150 ?m, and it is thereby possible to prevent a malfunction of a high side driver circuit of another phase to which no negative surge is applied.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: January 3, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masaharu Yamaji, Hideaki Katakura
  • Patent number: 9478543
    Abstract: A low side control circuit and a high side control circuit are disposed in first and second n type well regions, respectively. A third n? type well region is formed around the second n type well region. The first n? type well region is formed outside the second n? type well region. A p type well region is formed around the third n? type well region. The third n? type well region and the p type well region constitute an HVJT between the first and second n type well regions. A p+ type contact region and a first electrode supplied with GND potential are formed in the p type well region. In the p type well region, an n+ type contact region and a second electrode supplied with L-VDD potential higher than the GND potential are formed between the HVJT and the p+ type contact region.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: October 25, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu Yamaji
  • Publication number: 20160308534
    Abstract: A semiconductor integrated circuit device, including a semiconductor layer of a first conductivity type, a first well region of a second conductivity type, a second well region of the second conductivity type, and a third well region of the first conductivity type. The device further includes an isolation region electrically isolating a predetermined region in the first well region, a first high-concentration region of the second conductivity type, disposed outside the isolation region and inside one of the first well region and the second well region, and a second high-concentration region of the second conductivity type, disposed inside the isolation region and inside one of the first well region and the second well region. The first and second high-concentration regions each have an impurity concentration that is higher than that of the first well region.
    Type: Application
    Filed: June 29, 2016
    Publication date: October 20, 2016
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu YAMAJI
  • Publication number: 20160300912
    Abstract: A semiconductor device includes a resistive element wherein a diffusion resistance region provided in an upper portion of a semiconductor base and a thin film resistance layer isolated and distanced from the semiconductor base and diffusion resistance region across an insulating film are alternately connected in series and alternately disposed in parallel.
    Type: Application
    Filed: March 9, 2016
    Publication date: October 13, 2016
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide TANAKA, Masaharu YAMAJI
  • Patent number: 9443966
    Abstract: An n-type region encloses an n-type well region is disclosed in which is disposed a high-side drive circuit. A high resistance polysilicon thin film configuring a resistive field plate structure of a high breakdown voltage junction termination region is disposed in spiral form on the n-type region. An OUT electrode, a ground electrode, and a Vcc1 electrode are disposed on the n-type region. The Vcc1 electrode is connected to the positive electrode of an auxiliary direct current power supply (a bootstrap capacitor). The OUT electrode is connected to the negative electrode of the auxiliary direct current power supply. One end portion (a second contact portion) of the high resistance polysilicon thin film is connected to the ground electrode, and the other end portion (a first contact portion) of the high resistance polysilicon thin film is connected to the OUT electrode.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: September 13, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu Yamaji
  • Patent number: 9412732
    Abstract: In a high-side region, a first n-diffusion region, in which a PMOS constituting a gate drive circuit is formed, and a second n-diffusion region, in which a p-diffusion region is formed, are provided on a surface layer of a p?? substrate. An NMOS constituting a gate drive circuit is formed in the p-diffusion region. A p-type isolation diffusion region at ground potential is provided between the first n-diffusion region and the second n-diffusion region, and the first re-diffusion region and the second n-diffusion region are electrically isolated. The first n-diffusion region is connected to a VB terminal at a power source potential. The second n-diffusion region is connected to a terminal at a reference or floating potential. The p-diffusion region is connected to a VS terminal at a reference potential. Accordingly, it is possible to suppress parasitic operation due to a surge, without using external components, and without element breakdown.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: August 9, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masaharu Yamaji, Hiroshi Kanno