Abstract: Warping of a semiconductor wafer occurring due to a difference in the thermal expansion rates of an insulating film and the semiconductor wafer is restricted. Therefore, processing failures and conveying failures in the manufacturing process, as well as cracking of the semiconductor wafer, are restricted. Provided is a high breakdown voltage passive element including a substrate, a lower metal layer and upper metal layer stacked on the substrate, and an insulating unit formed between the lower metal layer and upper metal layer, wherein the insulating unit has a first insulating film whose thermal expansion rate is lower than the thermal expansion rate of the substrate, and a second insulating film, formed on the first insulating film, whose thermal expansion rate is higher than the thermal expansion rate of the substrate.

Abstract: An MV-PMOS and MV-NMOS configuring a high side drive circuit are formed in an n-type isolation region formed on a p-type semiconductor substrate. The MV-NMOS is connected to a p-type isolation region of an intermediate potential in the interior of the n-type isolation region. An n-type epitaxial region is provided in a surface layer of the p-type semiconductor substrate on the outer side of the n-type isolation region, and a p-type GND region of a ground potential (GND) is provided on the outer side of the n-type epitaxial region. A cavity is provided between the p-type semiconductor substrate and n-type epitaxial region between the high side drive circuit and p-type GND region, and a p-type diffusion region is provided penetrating the n-type epitaxial region and reaching the cavity. The intermediate potential is applied to the p-type isolation region.

Abstract: A semiconductor device includes a first conductive type first main electrode region, a first conductive type drift region which makes contact with the first main electrode region, a first conductive type second main electrode region which makes contact with the drift region, a second conductive type well region which is provided in a part of a surface layer portion of the drift region and to which a reference potential is applied, and a first conductive type potential extracting region which is provided in a surface layer portion of the well region and to which the reference potential is applied. The well region serves as a base region which controls a current flowing between the potential extracting region and the drift region. Thus, it is possible to provide a novel semiconductor device which is high in reliability while the increase of the chip size can be suppressed.

Abstract: A semiconductor device includes a high voltage isolation structure having a double RESURF structure. The high voltage isolation structure separates a low potential region from a high potential region. The high voltage isolation structure has an annular strip shape in a plan view and includes a straight portion and a corner portion which is connected to the straight portion. In the high voltage isolation structure, a p-type RESURF region is formed in a surface layer of a front surface of a substrate in an n-type well region along the outer circumference of the n-type well region. In the corner portion, the total amount of impurities per unit area in the RESURF region is less than that in the straight portion.

Abstract: In a semiconductor device including a bootstrap diode and a high voltage electric field transistor on a p-type semiconductor substrate, a cavity is formed in an n?-type buried layer of the semiconductor substrate to use the buried layer beneath the cavity as a drain drift region of the high voltage n-channel MOSFET, whereby a leakage current by holes that flows to the semiconductor substrate side in forward biasing of the bootstrap diode can be suppressed, and charging current for a bootstrap capacitor C1 can be increased, as well as increase in chip area can be suppressed.

Abstract: A semiconductor device is provided with a first well region of a first conduction type having a first voltage (voltage VB) applied thereto, a second well region of a second conduction type formed in the surface layer section of the first well region and having a second voltage (voltage VS) different from the first voltage applied thereto, and a charge extracting region of the first conduction type formed in the surface layer section of the second well region and having the first voltage applied thereto. This inhibits the operation of a parasitic bipolar transistor.

Abstract: A semiconductor device includes a first main electrode terminal and second main electrode terminal disposed on the principal surface of a semiconductor substrate so as to be spaced from one another, an insulating film formed on the principal surface of the semiconductor substrate, and a thin film resistance layer. One end side of the thin film resistance layer is connected to the first main electrode terminal and the other end side of the thin film resistance layer is connected to the second main electrode terminal, the thin film resistance layer being spirally formed on the insulating film in such a way as to surround the first main electrode terminal. The thin film resistance layer extends while oscillating in a thickness direction of the semiconductor substrate.

Abstract: In a high-side region, a first n-diffusion region, in which a PMOS constituting a gate drive circuit is formed, and a second n-diffusion region, in which a p-diffusion region is formed, are provided on a surface layer of a p?? substrate. An NMOS constituting a gate drive circuit is formed in the p-diffusion region. A p-type isolation diffusion region at ground potential is provided between the first n-diffusion region and the second n-diffusion region, and the first re-diffusion region and the second n-diffusion region are electrically isolated. The first n-diffusion region is connected to a VB terminal at a power source potential. The second n-diffusion region is connected to a terminal at a reference or floating potential. The p-diffusion region is connected to a VS terminal at a reference potential. Accordingly, it is possible to suppress parasitic operation due to a surge, without using external components, and without element breakdown.

Abstract: A low side control circuit and a high side control circuit are disposed in first and second n type well regions, respectively. A third n type well region is formed around the second n type well region. The first n? type well region is formed outside the second n? type well region. A p type well region is formed around the third n? type well region. The third n? type well region and the p type well region constitute an HVJT between the first and second n type well regions. A p+ type contact region and a first electrode supplied with GND potential are formed in the p type well region. In the p type well region, an n+ type contact region and a second electrode supplied with L-VDD potential higher than the GND potential are formed between the HVJT and the p+ type contact region.

Abstract: A semiconductor device and manufacturing method are disclosed which provide increased ESD resistance. By disposing a slit mask when forming a second p-type well layer, impurity concentration of the second p-type well layer is partially reduced. By forming a second n-type offset layer in the second p-type well layer having decreased impurity concentration, it is possible to increase thickness of the second n-type offset layer in this place compared with that heretofore known. By increasing thickness of the second n-type offset layer, a depletion layer does not reach an n-type drain layer at a low voltage when reverse bias is applied to the drain. It thus is possible to prevent thermal destruction caused by localized electrical field concentration. As a result, it is possible to increase ESD resistance. As it is sufficient to replace a photoresist mask, there is no increase in the number of processes.

Abstract: A withstand voltage region is formed to surround a logic circuit formation region. A high-voltage MOSFET for level shifting is formed in part of the withstand voltage region. A p? opening region is formed between a drain region of the high-voltage MOSFET and the logic circuit formation region. A shield layer connected to the negative electrode side of a power supply connected to the logic circuit formation region is disposed on the p? opening region. Thus, it is possible to provide a high-voltage semiconductor device including a level shifting circuit capable of making stable operation during the switching of a high-voltage IC and with long-term reliability.

Abstract: A high voltage integrated circuit device suppresses the quantity of holes that are implanted due to a negative voltage surge, thus preventing malfunction and destruction of a high side circuit. A p?-type aperture portion has a gap portion in an n-type well region that is a voltage resistant region, penetrating the n-type well region to reach a p-type substrate, so as to enclose an n-type well region that is a high potential region.

Abstract: In a semiconductor device such as a three-phase one-chip gate driver IC, HVNMOSs configuring two set and reset level shift circuits are disposed on non-opposed surfaces, and it is thereby possible to reduce the amount of electrons flowing into drains of HVNMOSs of another phase due to a negative voltage surge. Also, distances from an opposed surface on the opposite side to the respective drains of the HVNMOSs configuring the two set and reset level shift circuits are made equal to or more than 150 ?m, and it is thereby possible to prevent a malfunction of a high side driver circuit of another phase to which no negative surge is applied.

Abstract: An MV-PMOS and MV-NMOS configuring a high side drive circuit are formed in an n-type isolation region formed on a p-type semiconductor substrate. The MV-NMOS is connected to a p-type isolation region of an intermediate potential in the interior of the n-type isolation region. An n-type epitaxial region is provided in a surface layer of the p-type semiconductor substrate on the outer side of the n-type isolation region, and a p-type GND region of a ground potential (GND) is provided on the outer side of the n-type epitaxial region. A cavity is provided between the p-type semiconductor substrate and n-type epitaxial region between the high side drive circuit and p-type GND region, and a p-type diffusion region is provided penetrating the n-type epitaxial region and reaching the cavity. The intermediate potential is applied to the p-type isolation region.

Abstract: A semiconductor device includes a high voltage isolation structure having a double RESURF structure. The high voltage isolation structure separates a low potential region from a high potential region. The high voltage isolation structure has an annular strip shape in a plan view and includes a straight portion and a corner portion which is connected to the straight portion. In the high voltage isolation structure, a p-type RESURF region is formed in a surface layer of a front surface of a substrate in an n-type well region along the outer circumference of the n-type well region. In the corner portion, the total amount of impurities per unit area in the RESURF region is less than that in the straight portion.

Abstract: An n well region and an n?region surrounding the n well region are provided in the surface layer of a p?silicon substrate. The n?region includes breakdown voltage regions in which high voltage MOSFETs are disposed. The n well region includes a logic circuit region in which a logic circuit is disposed. A p? opening portion is provided between a drain region of each high voltage MOSFET and the logic circuit region. An n buffer region used as load resistances is provided between a second pick-up region and the drain region. The p?opening portion is provided between the n buffer region and logic circuit region. By so doing, it is possible to realize a reduction in the area of chips, and provide a high voltage semiconductor device having a level shift circuit with a high switching response speed.

Abstract: A semiconductor apparatus having a bootstrap-type driver circuit includes a cavity for a SON structure formed below a bootstrap diode Db, and a p-type floating region formed in a n? epitaxial layer between a bootstrap diode Db and a p-type GND region at the ground potential (GND). The p-type floating region extends to the cavity for suppressing the leakage current caused by the holes flowing to the p? substrate in charging an externally attached bootstrap capacitor C1. The semiconductor apparatus which includes a bootstrap-type driver circuit facilitates suppressing the leakage current caused by the holes flowing to the p? substrate, when the bootstrap diode is biased in forward.

Abstract: A withstand voltage region is formed to surround a logic circuit formation region. A high-voltage MOSFET for level shifting is formed in part of the withstand voltage region. A p? opening region is formed between a drain region of the high-voltage MOSFET and the logic circuit formation region. A shield layer connected to the negative electrode side of a power supply connected to the logic circuit formation region is disposed on the p? opening region. Thus, it is possible to provide a high-voltage semiconductor device including a level shifting circuit capable of making stable operation during the switching of a high-voltage IC and with long-term reliability.

Abstract: An n-type region encloses an n-type well region is disclosed in which is disposed a high-side drive circuit. A high resistance polysilicon thin film configuring a resistive field plate structure of a high breakdown voltage junction termination region is disposed in spiral form on the n-type region. An OUT electrode, a ground electrode, and a Vcc1 electrode are disposed on the n-type region. The Vcc1 electrode is connected to the positive electrode of an auxiliary direct current power supply (a bootstrap capacitor). The OUT electrode is connected to the negative electrode of the auxiliary direct current power supply. One end portion (a second contact portion) of the high resistance polysilicon thin film is connected to the ground electrode, and the other end portion (a first contact portion) of the high resistance polysilicon thin film is connected to the OUT electrode.

Abstract: A semiconductor device and manufacturing method are disclosed which provide increased ESD resistance. By disposing a slit mask when forming a second p-type well layer, impurity concentration of the second p-type well layer is partially reduced. By forming a second n-type offset layer in the second p-type well layer having decreased impurity concentration, it is possible to increase thickness of the second n-type offset layer in this place compared with that heretofore known. By increasing thickness of the second n-type offset layer, a depletion layer does not reach an n-type drain layer at a low voltage when reverse bias is applied to the drain. It thus is possible to prevent thermal destruction caused by localized electrical field concentration. As a result, it is possible to increase ESD resistance. As it is sufficient to replace a photoresist mask, there is no increase in the number of processes.