Patents by Inventor Masahiko Higashi

Masahiko Higashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11177252
    Abstract: The semiconductor device and the method of fabricating the same includes, on a surface of a semiconductor substrate 1 of a first conductivity type which is P-type or N-type, a diode element using a PN junction including a high-concentration first conductivity type impurity region 6 of the first conductivity type, a high-concentration second conductivity type impurity region 5 of a second conductivity type that is a conductivity type opposite to the first conductivity type, and an element isolation region 2 sandwiched between the high-concentration first conductivity type impurity region and the high-concentration second conductivity type impurity region, and a floating layer 3 of the second conductivity type separated from the high-concentration second conductivity type impurity region below the high-concentration second conductivity type impurity region on the semiconductor substrate.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: November 16, 2021
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Hiroyuki Tanaka, Masahiko Higashi
  • Publication number: 20210273249
    Abstract: A cell according to the present disclosure includes: a first electrode layer; a solid electrolyte layer on the first electrode layer, the solid electrolyte layer containing Zr; a middle layer on the solid electrolyte layer, the middle layer containing CeO2 which contains Ce and a rare earth element other than Ce; a second electrode layer on the middle layer; and a boundary region between the solid electrolyte layer and the middle layer, the boundary region including a basing point at which a molarity of Ce and a molarity of Zr are equal. An average molarity of the Ce within a range from the basing point up to 3 ?m toward the solid electrolyte layer is equal to or less than 10 mol % with respect to a total of Ce, Zr, and other rare earth elements, an average molarity of Zr within the range is equal to or more than 70 mol % with respect to a total of Ce, Zr, and other rare earth elements, or a molarity ratio of Ce with respect to Zr within the range is equal to or less than 0.143.
    Type: Application
    Filed: June 17, 2019
    Publication date: September 2, 2021
    Inventors: Tetsuro FUJIMOTO, Makoto KOI, Akihiro HARA, Masahiko HIGASHI
  • Patent number: 10812064
    Abstract: A device includes an epitaxial layer located over a semiconductor substrate, the epitaxial layer and the substrate both having a first conductivity type. A field-effect transistor (FET) includes source and drain regions having an opposite second conductivity type disposed in the epitaxial layer, and a gate structure over the substrate and between the source and drain regions. A diode includes first and second p-type regions and an n-type region all disposed in the epitaxial layer, the n-type region touching the first p-type region. A conductive plug electrically connects the first p-type region to the source region via the substrate.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: October 20, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Haian Lin, Frank Alexander Baiocchi, Masahiko Higashi, Namiko Hagane
  • Publication number: 20200312836
    Abstract: The semiconductor device and the method of fabricating the same includes, on a surface of a semiconductor substrate 1 of a first conductivity type which is P-type or N-type, a diode element using a PN junction including a high-concentration first conductivity type impurity region 6 of the first conductivity type, a high-concentration second conductivity type impurity region 5 of a second conductivity type that is a conductivity type opposite to the first conductivity type, and an element isolation region 2 sandwiched between the high-concentration first conductivity type impurity region and the high-concentration second conductivity type impurity region, and a floating layer 3 of the second conductivity type separated from the high-concentration second conductivity type impurity region below the high-concentration second conductivity type impurity region on the semiconductor substrate.
    Type: Application
    Filed: March 25, 2020
    Publication date: October 1, 2020
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Hiroyuki TANAKA, Masahiko Higashi
  • Publication number: 20200295748
    Abstract: A device includes an epitaxial layer located over a semiconductor substrate, the epitaxial layer and the substrate both having a first conductivity type. A field-effect transistor (FET) includes source and drain regions having an opposite second conductivity type disposed in the epitaxial layer, and a gate structure over the substrate and between the source and drain regions. A diode includes first and second p-type regions and an n-type region all disposed in the epitaxial layer, the n-type region touching the first p-type region. A conductive plug electrically connects the first p-type region to the source region via the substrate.
    Type: Application
    Filed: February 19, 2020
    Publication date: September 17, 2020
    Inventors: Haian Lin, Frank Alexander Baiocchi, Masahiko Higashi, Namiko Hagane
  • Patent number: 10581426
    Abstract: An electronic device includes a first semiconductor die with a first FET having a drain connected to a switching node, a source connected to a reference node, and a gate connected to a first switch control node. The first die also includes a diode-connected bipolar transistor that forms a temperature diode next to the first FET. The temperature diode includes a cathode connected to the reference node, and an anode connected to a bias node. The electronic device also includes a second semiconductor die with a second FET, and a package structure that encloses the first and second semiconductor dies.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: March 3, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Haian Lin, Frank Alexander Baiocchi, Masahiko Higashi, Namiko Hagane
  • Patent number: 10157903
    Abstract: A semiconductor device that improves the discharge capacity with respect to ESD without increasing the surface area of the semiconductor device includes a first conductive portion including plural portions, each of the plural portions having a first type of conductivity, and each of the plural portions extending in a first direction and being arranged in parallel at a distance from each other in a second direction that intersects the first direction; and a second conductive portion including an island portion provided between the respective plural portions of the first conductive portion and extending in the first direction, the second conductive portion having a second type of conductivity that is different from the first type of conductivity.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: December 18, 2018
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masahiko Higashi
  • Patent number: 9935320
    Abstract: A composite body includes a substrate containing Cr; and a first composite oxide layer disposed on at least a part of a surface of the substrate, the first composite oxide layer having a spinel type crystal structure, a first largest content and a second largest content among constituent elements excluding oxygen of the first composite oxide layer being Zn and Al in random order. Accordingly, the composite body can suppress diffusion of Cr from the substrate containing Cr to the first composite oxide layer, and has improved long-term reliability. A collector member and a gas tank, each of which is formed of the composite body, can have improved long-term reliability. A fuel cell device having excellent long-term reliability can be obtained using the collector member and the gas tank.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: April 3, 2018
    Assignee: KYOCERA CORPORATION
    Inventors: Tetsurou Fujimoto, Masahiko Higashi
  • Publication number: 20180061821
    Abstract: The present disclosure provides a semiconductor device that may improve the discharge capacity with respect to ESD without increasing the surface area of the semiconductor device. The semiconductor device includes: a first conductive portion including plural portions, each of the plural portions having a first type of conductivity, and each of the plural portions extending in a first direction and being arranged in parallel at a distance from each other in a second direction that intersects the first direction; and a second conductive portion including an island portion provided between the respective plural portions of the first conductive portion and extending in the first direction, the second conductive portion having a second type of conductivity that is different from the first type of conductivity.
    Type: Application
    Filed: August 23, 2017
    Publication date: March 1, 2018
    Inventor: MASAHIKO HIGASHI
  • Patent number: 9786927
    Abstract: To provide a conductive member and a cell stack, where a concave groove of a conductive base substrate can be covered with a cover layer, as well as an electrochemical module and an electrochemical device.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: October 10, 2017
    Assignee: Kyocera Corporation
    Inventor: Masahiko Higashi
  • Publication number: 20170162677
    Abstract: A semiconductor device fabricated by forming a dummy layer on a semiconductor substrate, forming a groove in the semiconductor substrate while using the dummy layer as a mask, forming a tunnel insulating film and a trap layer to cover an inner surface of the groove and the dummy layer, eliminating the trap layer formed above the upper surface and at the sides of the dummy layer, and forming a top insulating film to cover a remaining trap layer and the exposed tunnel insulating film.
    Type: Application
    Filed: February 17, 2017
    Publication date: June 8, 2017
    Inventor: Masahiko HIGASHI
  • Patent number: 9325019
    Abstract: A composite body in which the Cr diffusion can be sufficiently reduced and conductivity is good, a collector member, a fuel battery cell device, and a fuel battery device are provided. The composite body includes a substrate containing Cr, and a coating layer covering at least a part of the substrate, in which the coating layer includes a first layer containing Cr among constituent elements excluding oxygen, and including a chromium oxide crystal, a second layer disposed on the first layer, containing Zn, Al, and Cr among the constituent elements excluding oxygen, and including a spinel type crystal, a third layer disposed on the second layer, containing Zn and Mn among the constituent elements excluding oxygen, and including a spinel type crystal, and a fourth layer disposed on the third layer, containing Zn among the constituent elements excluding oxygen, and including a zinc oxide crystal.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: April 26, 2016
    Assignee: KYOCERA CORPORATION
    Inventors: Tetsuro Fujimoto, Masahiko Higashi
  • Publication number: 20150155571
    Abstract: [Object] To provide a conductive member and a cell stack, where a concave groove of a conductive base substrate can be covered with a cover layer, as well as an electrochemical module and an electrochemical device. [Solution] A conductive base substrate 41 made from an alloy containing Cr and a cover layer 43 covering the surface of the conductive base substrate 41 with chromium oxide 14 therebetween are included, wherein the conductive base substrate 41 includes a concave groove 15 extending from the surface toward the inside, the chromium oxide 14 is filled in the concave groove 15, and the surface of the chromium oxide 14 filled in the concave groove 15 is covered with the cover layer 43.
    Type: Application
    Filed: May 17, 2013
    Publication date: June 4, 2015
    Applicant: Kyocera Corporation
    Inventor: Masahiko Higashi
  • Patent number: 8993189
    Abstract: A heat-resistant alloy capable of effectively suppressing diffusion of Cr, as well as an alloy member for a fuel cell, a fuel cell stack device, a fuel cell module and a fuel cell device are provided. A heat-resistant alloy includes a Cr-containing alloy, and a Cr-diffusion suppression layer located on at least a part of a surface of the Cr-containing alloy, the Cr-diffusion suppression layer being made by laminating a first layer that contains a Zn-containing oxide and a second layer that does not contain ZnO but contains an (La, Sr)MnO3-based perovskite oxide in that order, so that it is possible to effectively suppress diffusion of Cr. By using the heat-resistant alloy for an alloy member for a fuel cell, a fuel cell stack device, a fuel cell module and a fuel cell device each having improved reliability can be obtained.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: March 31, 2015
    Assignee: Kyocera Corporation
    Inventors: Masahiko Higashi, Tetsurou Fujimoto, Norimitsu Fukami, Kenji Shimazu
  • Publication number: 20150086905
    Abstract: [Object] To provide a composite body in which the Cr diffusion can be sufficiently reduced and conductivity is good, a collector member, a fuel battery cell device, and a fuel battery device. [Solution] The composite body includes a substrate 200 containing Cr, and a coating layer 205 covering at least a part of the substrate 200, in which the coating layer 205 includes a first layer 201 containing Cr among constituent elements excluding oxygen, and including a chromium oxide crystal, a second layer 202 disposed on the first layer 201, containing Zn, Al, and Cr among the constituent elements excluding oxygen, and including a spinel type crystal, a third layer 203 disposed on the second layer 202, containing Zn and Mn among the constituent elements excluding oxygen, and including a spinel type crystal, and a fourth layer 204 disposed on the third layer 203, containing Zn among the constituent elements excluding oxygen, and including a zinc oxide crystal.
    Type: Application
    Filed: November 26, 2012
    Publication date: March 26, 2015
    Inventors: Tetsuro Fujimoto, Masahiko Higashi
  • Patent number: 8952536
    Abstract: A semiconductor memory device employs a SONOS type memory architecture and includes a bit line diffusion layer in a shallow trench groove in which a conductive film is buried. This makes it possible to decrease the resistivity of the bit line diffusion layer without enlarging the area on the main surface of the semiconductor substrate, and to fabricate the semiconductor memory device having stable electric characteristics without enlarging the cell area. The bit line is formed by implanting ions into the sidewall of Si3N4.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: February 10, 2015
    Assignee: Spansion LLC
    Inventors: Masahiko Higashi, Hiroyuki Nansei
  • Patent number: 8749012
    Abstract: Methods and structures for discharging plasma formed during the fabrication of semiconductor device are disclosed. The semiconductor device includes a wordline, a common ground line and a fuse structure for electrically coupling the wordline and the common ground line until a break signal is applied via the fuse structure.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: June 10, 2014
    Assignee: Spansion LLC
    Inventors: Masahiko Higashi, Naoki Takeguchi
  • Patent number: 8703350
    Abstract: The present invention provides a heat-resistant alloy member which hardly causes external diffusion of Cr, an alloy member for a fuel cell, a collector member for a fuel cell, a cell stack, and a fuel cell apparatus. The surface of a collector base material 201 containing Cr is coated with a Cr diffusion preventing layer 203 made of an oxide containing Zn and Mn and a coating layer 202 made of an oxide containing Zn is formed on the surface of the Cr diffusion preventing layer 203. The coating layer 202 preferably contains at least one kind of Al and Fe as a trivalent or higher valent positive metal element.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: April 22, 2014
    Assignee: Kyocera Corporation
    Inventors: Masahiko Higashi, Tetsuro Fujimoto
  • Patent number: 8669161
    Abstract: A device and method employing a polyoxide-based charge trapping component. A charge trapping component is patterned by etching a layered stack that includes a tunneling layer positioned on a substrate, a charge trapping layer positioned on the tunneling layer, and an amorphous silicon layer positioned on the charge trapping layer. An oxidation process grows a gate oxide layer from the substrate and converts the amorphous silicon layer into a polyoxide layer.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: March 11, 2014
    Assignee: Spansion LLC
    Inventor: Masahiko Higashi
  • Publication number: 20140021529
    Abstract: A method for manufacturing a semiconductor device, the method including: forming a bit line in a semiconductor substrate; forming a plurality of word lines which intersect with the bit line at predetermined intervals on the semiconductor substrate; eliminating a portion of the plurality of word lines; forming an interlayer insulating film on the semiconductor substrate; and forming a metal plug which penetrates through the interlayer insulating film and is coupled to the bit line in a region where the portion of the plurality of word lines was eliminated.
    Type: Application
    Filed: October 22, 2012
    Publication date: January 23, 2014
    Inventors: Naofumi TAKAHATA, Masahiko HIGASHI, Yukihiro UTSUNO