Abstract: A yielding percentage is calculated based on a first relationship, a probability distribution and a second relationship. The first relationship is a relationship between measurement values of a transfer pattern formed on a semiconductor substrate provided in the semiconductor device in the semiconductor lithographic process and number of sections on the semiconductor substrate where the measurement values are set. The probability distribution is a probability distribution showing variation of manufacturing parameters in the semiconductor lithographic process. The second relationship is a relationship between the manufacturing parameters and the measurement values.

Abstract: To provide a semiconductor device manufacturing method of making a pattern formation possible with high precision at a high speed, the same block can be completed by one process a cell by dividing the layout data into cells in the OPC processing step and then applying the OPC to each cell, and the OPC is applied only to the cell boundary portions after respective OPC-applied cells are arranged on the chip, so that a dimensional precision in vicinity of the cell boundaries can be ensured. Also, since the patterns on the cell boundary portions are caused to shrink uniformly, the OPC of the cell boundary portions can be simplified and thus the fast process can be applied.

Abstract: An object of the invention is to discover at the chip level a portion of a high density of contact holes in wires of a large area that becomes a portion where wire defects will occur. In order to achieve this, the area ratio of the total area of wires of the same node to the total area of contact holes in the wires of the same node is limited in a chip layout and wire formation defects are detected by determining whether or not defects exists based on this limitation. Thus, defects are detected wherein the area ratio exceeds the limit at the layout design stage and thereby formation defects such as a disconnection of a wire of a large area, a wire breakdown, a surface peeling due to a hillock or a defective connection between a wire and a contact hole can be avoided.

Abstract: A MOS transistor cell having a salicide structure has a plurality of gate wires each formed as a straight line with a constant width. Each of the gate wires includes a P-channel gate terminal and an N-channel gate terminal. The P-side ends and the N-side ends of the gate wires are connected by means of respective two gate wire connecting portions at a boundary portion between the MOS transistor cell and another adjacent MOS transistor cell.

Abstract: An object of the invention is to discover at the chip level a portion of a high density of contact holes in wires of a large area that becomes a portion where wire defects will occur. In order to achieve this, the area ratio of the total area of wires of the same node to the total area of contact holes in the wires of the same node is limited in a chip layout and wire formation defects are detected by determining whether or not defects exists based on this limitation. Thus, defects are detected wherein the area ratio exceeds the limit at the layout design stage and thereby formation defects such as a disconnection of a wire of a large area, a wire breakdown, a surface peeling due to a hillock or a defective connection between a wire and a contact hole can be avoided.