Patents by Inventor Masahiko Takenaka

Masahiko Takenaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160191387
    Abstract: It is determined whether or not the address of a first type specified in an address resolution query is an address that allows direct routing to a first network. If the direct routing is determined to be allowed, a routing table is configured such that a packet including, as a destination, the address of a second type obtained by the address resolution query is forwarded to the first network. If the direct routing is determined not to be allowed, the routing table is configured such that a packet including the obtained address of the second type as a destination is forwarded to a second network.
    Type: Application
    Filed: March 4, 2016
    Publication date: June 30, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Masahiko TAKENAKA, Kunikazu Matsumoto, Daisuke Shinomiya, YUTAKA TAKAHASHI, Hiroaki SAKAI
  • Publication number: 20160191408
    Abstract: A communication control apparatus includes a receiver and a processor. The receiver receives, from a first node, data including first identification information or second identification information. The processor generates a first authentication code by using first data when the receiver has received the first data including the first identification information. The receiver receives, from the first node, second data including the second identification information and a second authentication code that the first node has generated by using the first data. The processor decides whether to make the second node abort a process of the data reported using the first identification information, on the basis of a result of a comparison between the first authentication code and the second authentication code.
    Type: Application
    Filed: October 29, 2015
    Publication date: June 30, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Jun Yajima, Takayuki Hasebe, Masahiko TAKENAKA
  • Publication number: 20160171213
    Abstract: An apparatus stores first instructions including a call instruction and second instructions including a return instruction. When executing the second instructions called by the call instruction from the first instructions, the apparatus determines whether an instruction at a return address for return to the first instructions caused by the return instruction of the second instructions includes identification information. The apparatus continues processing of the first instructions when the instruction at the return address includes the identification information, and stops execution of the first instructions when the instruction at the return address does not include the identification information.
    Type: Application
    Filed: October 13, 2015
    Publication date: June 16, 2016
    Inventors: Kazuyoshi FURUKAWA, Hisashi Kojima, Masahiko TAKENAKA
  • Publication number: 20160173397
    Abstract: A communication control device includes ports, a memory, a processor, and a selector. The memory stores one or more pieces of identification information correlated with each of ports, the one or more pieces of identification information being included in a frame for transmission of the frame by communication devices each coupled to the ports. The processor generates a second frame in which is set second identification information regarding which determination will be made at the communication devices that the frame is to be discarded, when first identification information in a first frame received at a first port of the ports is not stored in the memory correlated with the first port. The selector selects only the second frame from among the first frame and the second frame when the first frame and the second frame are input, and outputs the selected second frame to the ports.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 16, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Jun YAJIMA, Masahiko TAKENAKA
  • Publication number: 20160147702
    Abstract: A communication control device includes a plurality of ports, a memory, and a processor. The memory stores one or more pieces of identification information correlated with each of one or more of the plurality of ports to which a communication device has been coupled, the one or more pieces of identification information being included in a frame for transmission of the frame by one or more communication devices each coupled to the one or more ports. The processor outputs, to the plurality of ports, a frame in which has been set second identification information regarding which determination will be made at the one or more communication devices that the frame is to be discarded, instead of the first identification information, when first identification information in a frame received at a first port of the one or more ports is not stored in the memory correlated with the first port.
    Type: Application
    Filed: November 18, 2015
    Publication date: May 26, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Jun YAJIMA, Masahiko Takenaka
  • Patent number: 9330270
    Abstract: An encryption processing device includes a memory configured to store a common key, and a processor configured to generate a random number which is an integer, to perform a bit transposition on the common key, the bit transposition being determined at least by the random number, to transmit the random number to another encryption processing device and to receive a response from the other encryption processing device, the response obtained by encryption using a common key stored in the other encryption processing device and a second randomized key generated by performing the bit transposition determined by the random number; and to authenticate the other encryption processing device either by comparing the response with the random number by decrypting the response with the common key, or by comparing the random number with the response by encrypting the random number with the common key.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: May 3, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Takao Ochiai, Kouichi Itoh, Dai Yamamoto, Kazuyoshi Furukawa, Masahiko Takenaka
  • Publication number: 20160110165
    Abstract: A quality detecting method, includes: storing, in a memory, an upper limit value and a lower limit value that specify a distribution range of a score corresponding to at least one type for each of variant random number sequences generated by shuffling an initial random number sequence; and causing a computer to: generate verification random number sequences; calculate a score corresponding to the type for each of the verification random number sequences; compare the scores of the verification random number sequences with the upper limit value and the lower limit value; acquire a frequency at which the scores of the verification random number sequences are distributed in the distribution range based on a comparison result; and detect, based on the frequency, quality of a physical random number generation circuit.
    Type: Application
    Filed: September 8, 2015
    Publication date: April 21, 2016
    Inventors: Hirotaka KOKUBO, Dai YAMAMOTO, Masahiko TAKENAKA, Kazuyoshi Furukawa
  • Patent number: 9319923
    Abstract: A node in an ad-hoc network includes a memory unit storing a concatenated counter value including an erasure counter value and a transmission counter value for the node; and a processor configured to: add one to the transmission counter value, when the node transmits data to another node in the ad-hoc network; transmit to the other node, the data and the updated concatenated counter value; detect erasure of the concatenated counter value in the memory unit; distribute in the ad-hoc network and upon detecting the erasure, an acquisition request for the erasure counter value; receive the erasure counter value consequent to the acquisition request; generate the concatenated counter value to include the received erasure counter value plus one and the transmission counter value after the erasure and indicating the number of transmissions as zero due to the erasure; and archive to the memory unit, the generated concatenated counter value.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: April 19, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuya Izu, Masahiko Takenaka, Hisashi Kojima, Kazuyoshi Furukawa
  • Patent number: 9313130
    Abstract: It is determined whether or not the address of a first type specified in an address resolution query is an address that allows direct routing to a first network. If the direct routing is determined to be allowed, a routing table is configured such that a packet including, as a destination, the address of a second type obtained by the address resolution query is forwarded to the first network. If the direct routing is determined not to be allowed, the routing table is configured such that a packet including the obtained address of the second type as a destination is forwarded to a second network.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: April 12, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Masahiko Takenaka, Kunikazu Matsumoto, Daisuke Shinomiya, Yutaka Takahashi, Hiroaki Sakai
  • Publication number: 20160057169
    Abstract: An apparatus includes a memory, and a processor coupled to the memory and configured to specify a communication source device that performs a plurality of traffic confirmations of communications with a plurality of first devices, and control to discard a plurality of first authentication requests for the plurality of first devices generated by the communication source device after performing the plurality of traffic confirmations of communications.
    Type: Application
    Filed: July 20, 2015
    Publication date: February 25, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Satomi Honda, Masahiko Takenaka, Satoru Torii
  • Publication number: 20150381348
    Abstract: An encryption processing method executed by a computer, the method includes converting a first vector using a first polynomial representation to acquire a first polynomial; converting an expression using a second polynomial representation to acquire a second polynomial, the expression being obtained based on a second vector and a random number corresponding to the first vector; converting the random number using at least one of the first polynomial representation and the second polynomial representation to acquire a random number polynomial; encrypting the first polynomial, the second polynomial, and the random polynomial using a homomorphic encryption scheme to acquire the encrypted first polynomial, the encrypted second polynomial, and the encrypted random polynomial; and collating the first vector and the second vector using the encrypted first polynomial, the encrypted second polynomial, and the encrypted random polynomial.
    Type: Application
    Filed: June 9, 2015
    Publication date: December 31, 2015
    Applicant: Fujitsu Limited
    Inventors: Masahiko TAKENAKA, Yumi Sakemi, MASAYA YASUDA
  • Patent number: 9203800
    Abstract: A communication method executed by a node in an ad hoc network having multiple nodes, includes receiving from a neighboring node of the node in the ad hoc network, a first packet that includes a sender address of the neighboring node and a first packet transmission count of packet transmissions from the neighboring node; extracting the first packet transmission count from the first packet; receiving from the neighboring node and after reception of the first packet, a second packet that includes the sender address of the neighboring node and a second packet transmission count of packet transmissions from the neighboring node; extracting the second packet transmission count from the second packet; determining whether the second packet is an invalid packet, based on the first packet transmission count and the second packet transmission count; and discarding the second packet upon determining the second packet to be an invalid packet.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: December 1, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuya Izu, Masahiko Takenaka, Kazuyoshi Furukawa, Hisashi Kojima
  • Patent number: 9166800
    Abstract: A method is disclosed for authenticating, by a processor that controls a parent device, a child device includes: authenticating the child device by making a comparison between a value obtained by operating, for a first response value, a third transform function, which is decided based on a number of a difference between the value set in an authentication chip of the parent device and the value set in an authentication chip of the child device, and the second response value, wherein a first and a second response values are obtained by operating a first and a second transform functions for output values generated by operating an encryption function for performing encryption for secret keys in authentication chips of the parent device and the child device, respectively.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: October 20, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Kouichi Itoh, Masahiko Takenaka
  • Publication number: 20150281188
    Abstract: A cryptographic processing apparatus that holds a first key, and receives authentication object data upon authentication includes a communication unit and a computing unit. The communication unit communicates with a calculation apparatus and a determination apparatus. In the calculation apparatus, encrypted registration data obtained by encrypting registration data twice, once with the first key and once with a second key, is registered. The registration data is data against which the authentication object data is verified. The determination apparatus uses the second key upon the authentication. When registering the encrypted registration data in the calculation apparatus, the computing unit generates a key different from the first key, generates encrypted data by encrypting the registration data twice, once with the first key and once with the different key, transmits the different key to the determination apparatus, and the encrypted data to the calculation apparatus, through the communication unit.
    Type: Application
    Filed: March 25, 2015
    Publication date: October 1, 2015
    Inventors: Yumi SAKEMI, Tetsuya IZU, Masahiko TAKENAKA
  • Publication number: 20150264075
    Abstract: A management method comprising, extracting, using a processor, psychological characteristics that are characteristic of people who have experienced a certain incident; extracting, using the processor, behavioral characteristics that are characteristic of people who have experienced a certain incident; obtaining, using the processor, a relational expression between each item of the extracted psychological characteristics and a plurality of items of the extracted behavioral characteristics; and calculating, using the processor, a psychological characteristic value from the relational expression of each psychological characteristic item and a value of log data for each user and, distributing, using the processor, to any user whose psychological characteristic value exceeds a predetermined value, a measure devised for the exceeded psychological characteristic.
    Type: Application
    Filed: February 25, 2015
    Publication date: September 17, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Takeaki TERADA, Yoshinori KATAYAMA, Masanobu MORINAGA, Masahiko TAKENAKA
  • Patent number: 9130745
    Abstract: A constant multiplier inputs a base and a modulo n, performs modular exponentiation modulo n with a prescribed constant as the exponent and with base a, and outputs the result of this calculation as base b. A personal key converter inputs a personal key d and calculates a personal key d? as the quotient when d is divided by the prescribed constant. A correction key generator generates a correction key d? as the remainder of the aforementioned division. A first modular exponentiation unit performs modular exponentiation base b with d? as the exponent. A second modular exponentiation unit performs modular exponentiation base a with d? as the exponent, and outputs a correction value. A correction calculation unit multiplies the outputs of the first and second modular exponentiation units and outputs the result as the encryption processing result.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: September 8, 2015
    Assignee: Fujitsu Limited
    Inventors: Kouichi Itoh, Dai Yamamoto, Masahiko Takenaka
  • Publication number: 20150207627
    Abstract: A semiconductor integrated circuit includes a first circuit configured to provide a predetermined function and a second circuit configured to have a physically unclonable function, wherein the second circuit is incorporated into the first circuit such that a signal value of at least one node in the first circuit varies in response to an output of the second circuit, and the output of the second circuit is set such that the first circuit provides the predetermined function.
    Type: Application
    Filed: January 9, 2015
    Publication date: July 23, 2015
    Inventors: Dai YAMAMOTO, Masahiko TAKENAKA
  • Publication number: 20150188704
    Abstract: A first random number receiver receives a first encrypted random number from a data communication apparatus. A second random number transmitter decrypts the first encrypted random number using a first private key to obtain a first random number, encrypts a second random number into a second encrypted random number using a second public key, and transmits it to the data communication apparatus. A hash value receiver receives a first hash value from the data communication apparatus. A session key generator generates a second hash value from the first random number decrypted with the first private key and the second random number, and generates a session key based on the first random number and the second random number when the first hash value is equal to the second hash value. In such key sharing communication, a data communication apparatus and another data communication apparatus achieve three-way handshake.
    Type: Application
    Filed: December 24, 2014
    Publication date: July 2, 2015
    Inventors: Masahiko TAKENAKA, Tetsuya IZU, Yumi SAKEMI
  • Patent number: 9071420
    Abstract: An information processing apparatus includes a processor configured to identify a data length that is longer than a data length of plain text data and that is a multiple of a predetermined block length; calculate a data length difference of the data length of the plain text and the data length; generate a first code that indicates the calculated data length difference; generate a second code that is calculated from the plain text data and is of a data length that is within a remaining data length acquired by subtracting a data length of the generated first code from the data length difference; create padding that includes the generated second code, has the first code at an end, and is of a length equivalent to the data length difference; concatenate the created padding to an end of the plain text data to generate concatenated data; and output the concatenated data.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: June 30, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Jun Yajima, Tetsuya Izu, Masahiko Takenaka
  • Publication number: 20150172064
    Abstract: A communication method is used in a relay device that is provided between a terminal and a server. The communication method includes: verifying a reliability of a server certificate that is transmitted from the server for cryptographic communication between the server and the relay device using a processor; issuing a proxy certificate based on the reliability of the server certificate for cryptographic communication between the relay device and the terminal using the processor; and transmitting the proxy certificate to the terminal.
    Type: Application
    Filed: December 1, 2014
    Publication date: June 18, 2015
    Inventors: Masahiko TAKENAKA, Daisuke Shinomiya, Hideki Ise