Patents by Inventor Masahiro Gion

Masahiro Gion has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210105009
    Abstract: A semiconductor integrated circuit device includes: first and second transistors provided between a first power source and an output terminal; a step-down circuit that generates a second power source from the first power source; a power source switch circuit that outputs, as a fourth power source, a higher one of potentials of the second power source and a third power source; and a level shifter circuit that transits between the first power source and a fourth power source. The first transistor has a gate connected to an output of the level shifter circuit; the second transistor has a gate connected to the fourth power source.
    Type: Application
    Filed: December 15, 2020
    Publication date: April 8, 2021
    Inventors: Masahisa IIDA, Masahiro GION
  • Patent number: 10355685
    Abstract: An output transistor (2) has a source connected to a VDD1 and a drain connected to an output terminal (1). A pre-driver (3) receives a signal varying in accordance with a data input signal (DIN), and provides a gate signal (SG1) to a gate of the output transistor (2), the gate signal (SG1) transiting between the VDD1 and a potential (VP) at a power source end (4). When a VDD2 is output from an output node (N1) and an assist signal (SA) makes a first transition corresponding to the transition of the gate signal (SG1) from HIGH to LOW, the drive assist circuit (20) performs an assist operation in which a potential of the output node (N1) is temporarily brought down from VDD2.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: July 16, 2019
    Assignee: SOCIONEXT INC.
    Inventors: Masahisa Iida, Masahiro Gion
  • Publication number: 20180287600
    Abstract: An output transistor (2) has a source connected to a VDD1 and a drain connected to an output terminal (1). A pre-driver (3) receives a signal varying in accordance with a data input signal (DIN), and provides a gate signal (SG1) to a gate of the output transistor (2), the gate signal (SG1) transiting between the VDD1 and a potential (VP) at a power source end (4). When a VDD2 is output from an output node (N1) and an assist signal (SA) makes a first transition corresponding to the transition of the gate signal (SG1) from HIGH to LOW, the drive assist circuit (20) performs an assist operation in which a potential of the output node (N1) is temporarily brought down from VDD2.
    Type: Application
    Filed: June 6, 2018
    Publication date: October 4, 2018
    Inventors: Masahisa IIDA, Masahiro GION
  • Patent number: 9479154
    Abstract: A semiconductor integrated circuit includes a power supply switch circuit which uses a PMOS transistor and an NMOS transistor to select a first power supply voltage applied to a first power supply input terminal or a second power supply voltage applied to a second power supply input terminal, and output the selected voltage as a power supply voltage to a third power supply output terminal, a first switch control circuit connected to the gate of the PMOS transistor, and a second switch control circuit connected to the gate of the NMOS transistor.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: October 25, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Daisuke Matsuoka, Masahiro Gion, Shiro Usami
  • Publication number: 20150171858
    Abstract: A semiconductor integrated circuit includes a power supply switch circuit which uses a PMOS transistor and an NMOS transistor to select a first power supply voltage applied to a first power supply input terminal or a second power supply voltage applied to a second power supply input terminal, and output the selected voltage as a power supply voltage to a third power supply output terminal, a first switch control circuit connected to the gate of the PMOS transistor, and a second switch control circuit connected to the gate of the NMOS transistor.
    Type: Application
    Filed: February 26, 2015
    Publication date: June 18, 2015
    Inventors: Daisuke MATSUOKA, Masahiro GION, Shiro USAMI
  • Patent number: 8502592
    Abstract: In a level shift circuit allows satisfactory operation with short delay time in the case of low-voltage setting of a low-voltage source, for example, when a state of an input signal IN transitions from a H (VDD) level to a L level, a node W2 precharged to a H (VDD3) level is discharged to ground (VSS) by a discharge circuit N2, and decreases in potential. The decrease in potential propagates to a latch circuit LA, and an output of the latch circuit LA propagates to an output circuit OC. Further, an inversion signal of the node W2 is input to the output circuit OC by bypassing the latch circuit LA. Thus, the output circuit OC starts operating prior to operation based on an output of the latch circuit LA.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: August 6, 2013
    Assignee: Panasonic Corporation
    Inventor: Masahiro Gion
  • Patent number: 8344786
    Abstract: A semiconductor integrated circuit includes a level shift circuit which is located so that a second IO cell region is interposed between the level shift circuit and a first IO cell region, and converts a signal output from an IO cell of the first IO cell region into a signal having an amplitude of a second voltage and outputs the resultant signal, and an internal circuit which is operated using the signal having the amplitude of the second voltage output from the level shift circuit. A signal interconnect via which the signal output from the IO cell of the first IO cell region is input to the level shift circuit is provided between the IO cell of the first IO cell region and the level shift circuit, extending over or in an IO cell of the second IO cell region.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: January 1, 2013
    Assignee: Panasonic Corporation
    Inventor: Masahiro Gion
  • Publication number: 20110285448
    Abstract: A semiconductor integrated circuit includes a level shift circuit which is located so that a second IO cell region is interposed between the level shift circuit and a first IO cell region, and converts a signal output from an IO cell of the first IO cell region into a signal having an amplitude of a second voltage and outputs the resultant signal, and an internal circuit which is operated using the signal having the amplitude of the second voltage output from the level shift circuit. A signal interconnect via which the signal output from the IO cell of the first IO cell region is input to the level shift circuit is provided between the IO cell of the first IO cell region and the level shift circuit, extending over or in an IO cell of the second IO cell region.
    Type: Application
    Filed: July 7, 2011
    Publication date: November 24, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: Masahiro GION
  • Patent number: 7768308
    Abstract: In a level shift circuit, the threshold voltage of N-type high-voltage transistors, to whose gates the voltage of a low-voltage supply VDD is applied, is set low. An input signal IN powered by the low-voltage supply VDD is input to the gate of an N-type transistor by way of an inverter. Therefore, even if the potentials at nodes W3 and W4 exceed the voltage of the low-voltage supply VDD, reverse current flow from the nodes W3 and W4 via parasitic diodes within the inverters into the low-voltage supply VDD is prevented. A protection circuit, composed of N-type transistor whose respective gates are fixed to the low-voltage supply VDD, is disposed between the two N-type high-voltage transistors N5, N6 and two N-type low-voltage transistors N1, N2 for receiving the complementary signals IN and XIN, thereby preventing the breakdown of those N-type complementary-signal-receiving transistors.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: August 3, 2010
    Assignee: Panasonic Corporation
    Inventors: Masato Maede, Naoki Nojiri, Masahiro Gion, Shinji Kinuyama, Daisuke Matsuoka, Shiro Usami
  • Publication number: 20080238481
    Abstract: In a level shift circuit, the threshold voltage of N-type high-voltage transistors, to whose gates the voltage of a low-voltage supply VDD is applied, is set low. An input signal IN powered by the low-voltage supply VDD is input to the gate of an N-type transistor by way of an inverter. Therefore, even if the potentials at nodes W3 and W4 exceed the voltage of the low-voltage supply VDD, reverse current flow from the nodes W3 and W4 via parasitic diodes within the inverters into the low-voltage supply VDD is prevented. A protection circuit, composed of N-type transistor whose respective gates are fixed to the low-voltage supply VDD, is disposed between the two N-type high-voltage transistors N5, N6 and two N-type low-voltage transistors N1, N2 for receiving the complementary signals IN and XIN, thereby preventing the breakdown of those N-type complementary-signal-receiving transistors.
    Type: Application
    Filed: June 4, 2008
    Publication date: October 2, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masato MAEDE, Naoki Nojiri, Masahiro Gion, Shinji Kinuyama, Daisuke Matsuoka, Shiro Usami
  • Publication number: 20080230918
    Abstract: A semiconductor integrated circuit, including an input/output cell including signal terminals, wherein the signal terminal of the input/output cell is connected to an internal circuit via an interconnect wiring. The signal terminal of the I/O cell includes a plurality of (e.g., four) conductive layers. Each pair of adjacent ones of the plurality of conductive layers are connected together by a via. One of the plurality of conductive layers to which a via of the largest diameter is connected (e.g., the fourth conductive layer) is formed with a width such that only one of the largest-diameter via can be accommodated. Therefore, it is possible to suppress the migration of atoms from the interconnect wiring to the input terminal of the I/O cell, and to suppress the open failure of the via formed on the interconnect wiring.
    Type: Application
    Filed: March 14, 2008
    Publication date: September 25, 2008
    Inventor: Masahiro Gion
  • Patent number: 7423472
    Abstract: There is provided a power switching circuit capable of completely breaking a current in an OFF state of a switch connecting power sources even when a voltage difference is generated between the power sources of a plurality of functional blocks separated from each other on an LSI chip. A gate control circuit 1a has a control signal terminal INCNT, a first power imputer terminal IG11, and a second power supply terminal IG12 as input terminals and has a first output terminal OG11 and a second output terminal OG12 as output terminals. The gate of a second P-type transistor P2 is connected to the first output terminal OG11 of the gate control circuit 1a and the gate of a second P-type transistor P2 is connected to the second output terminal OG12 of the gate control circuit 1a, wherein the first P-type transistor P1 and the second P-type transistor P2 are connected in series between a first power source VDD1 and a second power source VDD2 to form a switch section.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: September 9, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaya Hirose, Kinya Daio, Masahiro Gion, Masato Maede, Hisaki Watanabe
  • Publication number: 20070247210
    Abstract: In a level shift circuit, the threshold voltage of N-type high-voltage transistors, to whose gates the voltage of a low-voltage supply VDD is applied, is set low. An input signal IN powered by the low-voltage supply VDD is input to the gate of an N-type transistor by way of an inverter. Therefore, even if the potentials at nodes W3 and W4 exceed the voltage of the low-voltage supply VDD, reverse current flow from the nodes W3 and W4 via parasitic diodes within the inverters into the low-voltage supply VDD is prevented. A protection circuit, composed of N-type transistor whose respective gates are fixed to the low-voltage supply VDD, is disposed between the two N-type high-voltage transistors N5, N6 and two N-type low-voltage transistors N1, N2 for receiving the complementary signals IN and XIN, thereby preventing the breakdown of those N-type complementary-signal-receiving transistors.
    Type: Application
    Filed: June 13, 2007
    Publication date: October 25, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masato Maede, Naoki Nojiri, Masahiro Gion, Shinji Kinuyama, Daisuke Matsuoka, Shiro Usami
  • Publication number: 20060214722
    Abstract: There is provided a power switching circuit capable of completely breaking a current in an OFF state of a switch connecting power sources even when a voltage difference is generated between the power sources of a plurality of functional blocks separated from each other on an LSI chip. A gate control circuit 1a has a control signal terminal INCNT, a first power imputer terminal IG11, and a second power supply terminal IG12 as input terminals and has a first output terminal OG11 and a second output terminal OG12 as output terminals. The gate of a second P-type transistor P2 is connected to the first output terminal OG11 of the gate control circuit 1a and the gate of a second P-type transistor P2 is connected to the second output terminal OG12 of the gate control circuit 1a, wherein the first P-type transistor P1 and the second P-type transistor P2 are connected in series between a first power source VDD1 and a second power source VDD2 to form a switch section.
    Type: Application
    Filed: March 28, 2006
    Publication date: September 28, 2006
    Inventors: Masaya Hirose, Kinya Daio, Masahiro Gion, Masato Maede, Hisaki Watanabe
  • Publication number: 20050134355
    Abstract: In a level shift circuit, the threshold voltage of N-type high-voltage transistors, to whose gates the voltage of a low-voltage supply VDD is applied, is set low. An input signal IN powered by the low-voltage supply VDD is input to the gate of an N-type transistor by way of an inverter. Therefore, even if the potentials at nodes W3 and W4 exceed the voltage of the low-voltage supply VDD, reverse current flow from the nodes W3 and W4 via parasitic diodes within the inverters into the low-voltage supply VDD is prevented. A protection circuit, composed of N-type transistor whose respective gates are fixed to the low-voltage supply VDD, is disposed between the two N-type high-voltage transistors N5, N6 and two N-type low-voltage transistors N1, N2 for receiving the complementary signals IN and XIN, thereby preventing the breakdown of those N-type complementary-signal-receiving transistors.
    Type: Application
    Filed: December 3, 2004
    Publication date: June 23, 2005
    Inventors: Masato Maede, Naoki Nojiri, Masahiro Gion, Shinji Kinuyama, Daisuke Matsuoka, Shiro Usami
  • Patent number: 6873186
    Abstract: In a level shift circuit, for example, when an input signal IN changes from the L level to the H level, an N-type signal input transistor is made conducting and current flows in the N-type transistor. Accordingly, a first current mirror circuit amplifies the current flowing in the N-type transistor by predetermined number of times, increases the current driving capability for an inverted output node, and changes the inverted output node quickly to the L level. With the change to the L level of the inverted output node, an output node changes to the H level, a P-type transistor (first current interrupting circuit) is made non-conducting by the change, and the current fed from the first current mirror circuit is interrupted. Therefore, even when the power source voltage for the input signal and the inverted input signal is lowered, the operation is performed at high speed.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: March 29, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Masahiro Gion
  • Patent number: 6853228
    Abstract: In a flip-flop circuit which includes an input section using a dynamic circuit and an output section using a static circuit and which captures data during a period of a pulse width shorter than a clock cycle, the number of transistors, circuit area and power consumption are reduced. In FIG. 1, an output signal of an inverter circuit INV1 constituting a latch circuit 2 connected to the output terminal of an input section 1 is used as an input signal of a control section 3. Thus, a control signal output from the control section 3 to the input section 1 is stabilized, thereby suppressing unnecessary operation of circuit elements and reducing unnecessary power consumption. In addition, the configuration of the control section 3 is simplified. As a result, the number of transistors constituting the circuit and the circuit area can be reduced.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: February 8, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akio Hirata, Masahiro Gion, Kazuyuki Nakanishi
  • Publication number: 20050007148
    Abstract: In a level shift circuit, for example, when an input signal IN changes from the L level to the H level, an N-type signal input transistor is made conducting and current flows in the N-type transistor. Accordingly, a first current mirror circuit amplifies the current flowing in the N-type transistor by predetermined number of times, increases the current driving capability for an inverted output node, and changes the inverted output node quickly to the L level. With the change to the L level of the inverted output node, an output node changes to the H level, a P-type transistor (first current interrupting circuit) is made non-conducting by the change, and the current fed from the first current mirror circuit is interrupted. Therefore, even when the power source voltage for the input signal and the inverted input signal is lowered, the operation is performed at high speed.
    Type: Application
    Filed: June 8, 2004
    Publication date: January 13, 2005
    Inventor: Masahiro Gion
  • Patent number: 6791391
    Abstract: In a CMOS level shifting circuit including N-channel transistors that have sources to which a digital signal is supplied, a bias voltage Vref is supplied to gates of the N-channel transistors, and the bias voltage Vref is set to be higher than a high level voltage of the digital signal and lower than a value obtained by adding a threshold voltage of the N-channel transistors to the high level voltage of the digital signal. Thus, a level shifting circuit is provided that is capable of outputting a signal having subjected to stable level conversion, even when a voltage level of a low voltage signal is lowered.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: September 14, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hidetoshi Nishimura, Masahiro Gion, Heiji Ikoma, Naoki Nojiri
  • Publication number: 20040080351
    Abstract: In a flip-flop circuit which includes an input section using a dynamic circuit and an output section using a static circuit and which captures data during a period of a pulse width shorter than a clock cycle, the number of transistors, circuit area and power consumption are reduced.
    Type: Application
    Filed: October 17, 2003
    Publication date: April 29, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO.
    Inventors: Akio Hirata, Masahiro Gion, Kazuyuki Nakanishi