Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A data processing method for compressing vertex coordinate data of a plurality of polygons approximating a three-dimensional shape of an image, an apparatus therefor, and a program recording medium therefor. Vertexes of a plurality of polygons approximating a three-dimensional shape of an image are divided into a plurality of vertex sets. A reference point is defined for each of the vertex sets. As positional information of each vertex in each of the vertex sets, differential data between the coordinates of the vertex and the coordinates of the reference point is obtained as an integer value indicating the magnitude relative to a predetermined scale value. The coordinate data of the reference point and the differential data in each of the vertex sets are compressed data.

Abstract: Disclosed here is a data processor provided with an addressing mode for calculating each effective address from the displacement (reference address) included in the subject instruction and the information retained in an index register allocated to a general-purpose register so as to minimize an increase of the logical/physical scale. The value in the index register is increased so as to be shifted according to the memory access size, for example, by one when the memory access size is byte and by two when the memory access size is word. Because both extension and shifting are included in the effective address calculation, the number of instructions, as well as the number of execution states are reduced. And, because the array size is smaller than the address space size, the upper part of each general-purpose register is used as a data register, thereby the data amount to be written in each general-purpose register is increased and the number of times for reading/writing from/in the subject memory is reduced.

Abstract: To eliminate pipeline stall due to data hazard in a superscalar system and to increase the processing speed. An instruction decoder is provided with a circuit which detects two neighboring 2-operand instructions which are equivalent to one 3-operand instruction, and a circuit which, if it is equivalent, integrates the two instructions into the 3-operand instruction and sends it to a succeeding execution stage. Or, provision is made of a circuit which sends the source data of a preceding instruction to an arithmetic unit for a succeeding instruction when the two neighboring instructions have a relationship of data flow but cannot be integrated into one 3-operand instruction. It is allowed to execute the processing of two instructions in one clock, which so far required two clocks due to data flow between the neighboring instructions. Therefore, the number of execution clocks as a whole can be decreased.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Abstract: A data processing method for compressing vertex coordinate data of a plurality of polygons approximating a three-dimensional shape of an image, an apparatus therefor, and a program recording medium therefor. Vertexes of a plurality of polygons approximating a three-dimensional shape of an image are divided into a plurality of vertex sets. A reference point is defined for each of the vertex sets. As positional information of each vertex in each of the vertex sets, differential data between the coordinates of the vertex and the coordinates of the reference point is obtained as an integer value indicating the magnitude relative to a predetermined scale value. The coordinate data of the reference point and the differential data in each of the vertex sets are compressed data.

Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Abstract: A microcomputer CMU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Abstract: A branch instruction format has different respective field lengths for conditional branch instructions and unconditional branch instructions. A conditional branch instruction has a first bit length and a first area for a displacement designating an address to be jumped, wherein the first area has a second bit length that is smaller than the first bit length. An unconditional branch instruction also has the first bit length, and a second area for a displacement designating an address to be jumped, wherein the second area has a third bit length that is different from the first and second bit lengths.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Abstract: Particular portions of a program is determined to execute repeatedly. Array references accessed in a loop are classified to groups of equal values on the basis of reference to the same array. Of the groups, the ones for which an array transposition can use a batch load or store instruction are selected. An array corresponding to the selected groups is transposed to generate an intermediate language for copying. Reference to the elements of the array before the transposition is changed to reference to the transposition array. This makes it possible to convert the loop so that a single instruction can be used for a processor which can load into a register two data having consecutive addresses in a memory with use of the instruction.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A division method and circuit performs a division for signed data by adding or subtracting a divisor to or from the dividend or the partial remainder from the division, according to the sign of the divisor or the dividend and the partial remainder to acquire a new partial remainder. The division is repeated a predetermined number of times in which a quotient bit is acquired according to the sign of the acquired partial remainder or the divisor. The dividend is corrected by subtracting 1, which is the significance of an LSB of the corresponding dividend, from the dividend when the sign of the dividend is negative, and the corrected dividend is used for the division processing.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A control system for a cache provided between a central processing unit and a main memory. The control system includes a plurality of entries each having a data area and a control information area. A reuse information field in the control information area is set at the same time as a load/store instruction from the central processing unit. When the central processing unit issues an access instruction to desired data in the main memory, an entry storing the desired data to be accessed is searched from a plurality of entries of the cache. If the desired data is not present in any of the plurality of entries, the desired data is read from the main memory. Then, an empty entry is searched from the plurality of entries. If there is no empty entry, an entry is selected which is not set with the reuse information in the control information area of the entry, the reuse information instructing to preferentially maintaining the data in the data field of the entry.