Patents by Inventor Masahiro Kanazawa

Masahiro Kanazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030102898
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Application
    Filed: January 14, 2003
    Publication date: June 5, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa
  • Publication number: 20030088836
    Abstract: A low power test circuit and a semiconductor integrated circuit are provided, i.e., the low power test circuit comprises a first stage single phase scan flip flop, a second stage single phase scan flip flop, a delay element located between an output terminal of the first stage single phase scan flip flop and an input terminal of the second stage single phase scan flip flop, a gate circuit connected between the output terminal of the first stage single phase scan flip flop and the delay element, and the gate circuit transferring scan data from the output terminal of the first stage single phase scan flip flop to the delay element in a scanning test mode thus reducing power dissipation in the delay element. The semiconductor integrated circuit comprises a shift register comprising a plurality of single phase scan flip flop serially connected and the low power test circuit.
    Type: Application
    Filed: October 29, 2002
    Publication date: May 8, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masahiro Kanazawa, Kimiyoshi Usami, Naoyuki Kawabe, Takeshi Kitahara
  • Patent number: 6493856
    Abstract: An automatic circuit generation methods and apparatus (1) provide a desired circuit performance by reducing a leakage current during both a standby state and an active state, where cells having only High-Vth and Mt cells having both High-Vth transistors and Low-Vth translators are optimally mixed in a logical circuit. It is thereby possible to suppress efficiently the leakage current, in a design stage, generated according to miniaturization of LSI layout design and also lowering a supply voltage to the LSI.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: December 10, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kimiyoshi Usami, Naoyuki Kawabe, Masahiro Kanazawa, Masayuki Koizumi, Hidemasa Zama, Toshiyuki Furusawa
  • Publication number: 20020144223
    Abstract: A logic circuit design equipment has a state analysis section, a leakage current analysis section, and a cell substitution section. The state analysis section has a function of analyzing input states of all of first cells, respectively. The leakage current analysis section has a function of analyze leakage currents of all of first cells in a case where each first cell is high Vth cell showing a small leakage current at a low speed operation and low Vth cell showing a large leakage current at a high speed operation, respectively. The cell substitution section has a function of substituting the first cells for second cells within a range satisfying a timing restriction. Herein, a threshold of the second cell is different from a threshold of the first cell.
    Type: Application
    Filed: April 1, 2002
    Publication date: October 3, 2002
    Inventors: Kimiyoshi Usami, Naoyuki Kawabe, Takeshi Kitahara, Masahiro Kanazawa
  • Publication number: 20020036529
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Application
    Filed: September 21, 2001
    Publication date: March 28, 2002
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa
  • Publication number: 20020008545
    Abstract: There is provided a semiconductor integrated circuit, a logic operation circuit and a flip flop capable of operating at a high speed and having a leak electric current reduced.
    Type: Application
    Filed: June 20, 2001
    Publication date: January 24, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hidemasa Zama, Masayuki Koizumi, Yukiko Ito, Kimiyoshi Usami, Naoyuki Kawabe, Masahiro Kanazawa, Toshiyuki Furusawa
  • Publication number: 20020002701
    Abstract: An automatic circuit generation methods and apparatus (1) provide a desired circuit performance by reducing a leakage current during both a standby state and an active state, where cells having only High-Vth and Mt cells having both High-Vth transistors and Low-Vth translators are optimally mixed in a logical circuit. It is thereby possible to suppress efficiently the leakage current, in a design stage, generated according to miniaturization of LSI layout design and also lowering a supply voltage to the LSI.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 3, 2002
    Inventors: Kimiyoshi Usami, Naoyuki Kawabe, Masahiro Kanazawa, Masayuki Koizumi, Hidemasa Zama, Toshiyuki Furusawa
  • Patent number: 6266798
    Abstract: There are disclosed a multi power supply integrated circuit evaluating method which is capable of detecting power supply voltage illegal connection, redundant connection, and potential redundant connection from connection descriptions contained in a multi power supply integrated circuit in the stage of circuit design and then correcting automatically such connections, and a system for embodying the same.
    Type: Grant
    Filed: May 12, 1999
    Date of Patent: July 24, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Kanazawa, Kimiyoshi Usami
  • Patent number: 6097043
    Abstract: A semiconductor integrated circuit, a supply method of supplying multiple supply voltages therefor, and a record medium for storing a program of the supply method for supplying multiple voltages therefore in which a first cell to which multiple supply voltages are supplied is extracted (Step S1), the extracted cells are divided into groups (Step S2), cells for voltage supply are added and arranged according to the number of the groups (Step S3), and the cell for the voltage supply are connected to the first cell for supplying the plurality of voltages through a net for a power source supply (Step S4).
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: August 1, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mutsunori Igarashi, Hiroshi Tanaka, Kimiyoshi Usami, Takashi Ishikawa, Masahiro Kanazawa, Chiharu Mizuno
  • Patent number: 5920089
    Abstract: There is disclosed a multi-power supply integrated circuit including a first pMOS transistor which is formed in a first n-well and operated at a first supply voltage and a second pMOS transistor which is formed in a second n-well and operated at a second supply voltage being lower than the first supply voltage, wherein the first n-well and the second n-well are placed adjacently to put a boundary line therebetween and also the first supply voltage is supplied to both the first and second n-wells. Because a space between the first and second n-wells is made small, a gate array LSI with a reduced chip area is provided. A common n-well may be formed in place of the first and second n-wells.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: July 6, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Kanazawa, Kimiyoshi Usami
  • Patent number: 5362951
    Abstract: A reversing board 14 with a magnetic head 16 mounted thereon is provided at its central portion with card guides 14b1, 14b2 , the inlet ports of the card guides 14b1, 14b2 being disposed proximate to the front end openings of front and rear card guides 2A, 2B, the magnetic head 16 being biased by a compression spring 17S so that the head can be acted upwardly and downwardly, a positioning stopper 15 being engaged in a positioning groove 14a of the reversing board 14, a rotational tension force being exerted to a head reversing gear 12 by a tension spring 13S.
    Type: Grant
    Filed: March 24, 1992
    Date of Patent: November 8, 1994
    Assignee: Amano Corporation
    Inventors: Masahiro Kanazawa, Takeshi Miyashita