Abstract: A chemically amplified positive resist composition is provided comprising a polymer comprising units containing a phenolic hydroxy group and units containing a phenolic hydroxy group protected with an acid labile group, in which a carbon atom neighboring the carbon atom to which the phenolic hydroxy group protected with an acid labile group is attached is substituted with a specific group. A resist pattern with a high resolution, reduced LER, rectangularity, minimized influence of develop loading, and few development residue defects can be formed.

Abstract: A chemically amplified positive resist composition comprising (A) a base polymer, (B) a photoacid generator, and (C) a quencher is provided. The base polymer (A) contains a polymer comprising phenolic hydroxy group-containing units, aromatic ring-containing units, and units containing a phenolic hydroxy group protected with an acid labile group. The photoacid generator (B) and the quencher (C) are present in a weight ratio (B)/(C) of less than 3/1. The resist composition exhibits a very high isolated-space resolution and forms a pattern with reduced LER, rectangularity, minimized influences of develop loading and residue defects.

Abstract: The measuring instrument includes a sensor unit that measures a predetermined physical quantity; an amplifier circuit that amplifies a signal output from the sensor unit; and a linear power supply that supplies power to the amplifier circuit, in which the amplifier circuit includes a first amplifier having a first transistor using a SiC semiconductor, the linear power supply includes a second amplifier having a second transistor using the SiC semiconductor, and noise characteristics of the first amplifier are superior to noise characteristics of the second amplifier.

Abstract: Provided is a SiC semiconductor element equipped with a SiC integrated circuit having a stable characteristic, which operates normally even in a radiation environment. A radiation resistant circuit device includes: a SiC semiconductor element equipped with a SiC integrated circuit, a printed board on which the SiC semiconductor element is provided, a conductive wiring that is arranged inside the printed board and has a predetermined surface facing a bottom surface of a substrate electrode of the SiC integrated circuit, and an insulating material arranged between the bottom surface of the substrate electrode of the SiC integrated circuit and the predetermined surface of the conductive wiring.

Abstract: A semiconductor device includes an electrostatic protection circuit 1 and a MOSFET 2 including a gate terminal. The electrostatic protection circuit 1 includes a positive-side power supply terminal 3, a negative-side power supply terminal 5, a first protection diode 4, a second protection diode 6, a resistance element 7, and a bipolar transistor 8. The second protection diode 6 includes an anode terminal electrically connected to the negative-side power supply terminal 5 via the resistance element 7, and a cathode terminal electrically connected to the gate terminal. The bipolar transistor 8 includes a base terminal, an emitter terminal, and a collector terminal. The bipolar transistor 8 is electrically connected to the anode terminal of the second protection diode 6, the gate terminal, and the positive-side power supply terminal 3. The electrostatic protection circuit 1 is formed on a semiconductor substrate made of silicon carbide.

Abstract: The purpose of the present invention is to provide a semiconductor device comprising an epitaxial layer formed on a SiC substrate, and a CMOS formed in the top part of the epitaxial layer, wherein growth of any defects present at the interface between the SiC substrate and the epitaxial layer is suppressed, and the reliability of the semiconductor device is improved. As a means to achieve the foregoing, a semiconductor device is formed such that the distance from a p-type diffusion layer to the interface between an n-type epitaxial layer and an n-type semiconductor substrate is larger than the thickness of a depletion layer that extends from the p-type diffusion layer to the back side of the n-type semiconductor substrate in response to the potential difference between a substrate electrode and another substrate electrode.

Abstract: An n type semiconductor layer is formed over an n type semiconductor substrate made of silicon carbide, a p type impurity region is formed in the semiconductor layer, and an n type drain region and an n type source region are formed in the impurity region. A field insulating film having an opening that selectively opens a part of the impurity region located between the drain and source regions is formed over the impurity region and the drain and source regions. A gate insulating film is formed over the impurity region in the opening, and a gate electrode is formed on the gate insulating film. Here, a field relaxation layer having an impurity concentration higher than that of the impurity region is formed in at least a part of the impurity region located between the drain and source regions in plan view and located below the field insulating film.

Abstract: A semiconductor device includes an electrostatic protection circuit 1 and a MOSFET 2 including a gate terminal. The electrostatic protection circuit 1 includes a positive-side power supply terminal 3, a negative-side power supply terminal 5, a first protection diode 4, a second protection diode 6, a resistance element 7, and a bipolar transistor 8. The second protection diode 6 includes an anode terminal electrically connected to the negative-side power supply terminal 5 via the resistance element 7, and a cathode terminal electrically connected to the gate terminal. The bipolar transistor 8 includes a base terminal, an emitter terminal, and a collector terminal. The bipolar transistor 8 is electrically connected to the anode terminal of the second protection diode 6, the gate terminal, and the positive-side power supply terminal 3. The electrostatic protection circuit 1 is formed on a semiconductor substrate made of silicon carbide.

Abstract: A MOSFET that has a drain region and a source region on an upper surface of a semiconductor substrate and a gate electrode that is formed on the semiconductor substrate, and an element separation insulating film that includes an opening portion which exposes an active region, on the semiconductor substrate, are formed. At this point, a gate leading-out interconnection that overlaps the element separation insulating film when viewed from above, and that is integrally combined with the gate electrode is formed in a position where the gate leading-out interconnection does not extend over a distance between both the drain region and the source region when viewed from above, on a region that is exposed from the gate electrode.

Abstract: Provided is a SiC semiconductor element equipped with a SiC integrated circuit having a stable characteristic, which operates normally even in a radiation environment. A radiation resistant circuit device includes: a SiC semiconductor element equipped with a SiC integrated circuit, a printed board on which the SiC semiconductor element is provided, a conductive wiring that is arranged inside the printed board and has a predetermined surface facing a bottom surface of a substrate electrode of the SiC integrated circuit, and an insulating material arranged between the bottom surface of the substrate electrode of the SiC integrated circuit and the predetermined surface of the conductive wiring.

Abstract: An n type semiconductor layer is formed over an n type semiconductor substrate made of silicon carbide, a p type impurity region is formed in the semiconductor layer, and an n type drain region and an n type source region are formed in the impurity region. A field insulating film having an opening that selectively opens a part of the impurity region located between the drain and source regions is formed over the impurity region and the drain and source regions. A gate insulating film is formed over the impurity region in the opening, and a gate electrode is formed on the gate insulating film. Here, a field relaxation layer having an impurity concentration higher than that of the impurity region is formed in at least a part of the impurity region located between the drain and source regions in plan view and located below the field insulating film.

Abstract: A MOSFET that has a drain region and a source region on an upper surface of a semiconductor substrate and a gate electrode that is formed on the semiconductor substrate, and an element separation insulating film that includes an opening portion which exposes an active region, on the semiconductor substrate, are formed. At this point, a gate leading-out interconnection that overlaps the element separation insulating film when viewed from above, and that is integrally combined with the gate electrode is formed in a position where the gate leading-out interconnection does not extend over a distance between both the drain region and the source region when viewed from above, on a region that is exposed from the gate electrode.

Abstract: The purpose of the present invention is to provide a semiconductor device comprising an epitaxial layer formed on a SiC substrate, and a CMOS formed in the top part of the epitaxial layer, wherein growth of any defects present at the interface between the SiC substrate and the epitaxial layer is suppressed, and the reliability of the semiconductor device is improved. As a means to achieve the foregoing, a semiconductor device is formed such that the distance from a p-type diffusion layer to the interface between an n-type epitaxial layer and an n-type semiconductor substrate is larger than the thickness of a depletion layer that extends from the p-type diffusion layer to the back side of the n-type semiconductor substrate in response to the potential difference between a substrate electrode and another substrate electrode.

Abstract: There is provided a semiconductor device that improves reliability. The impurity concentrations of a p++ source region and a p++ drain region are 5×1020 cm?3 or more. The channel-region-side end portion of a first insulating film is disposed on a p+ source region. The end portion has an inclined surface where the first insulating film thickness is reduced from the p+ source region toward a channel region. The channel-region-side end portion of a second insulating film is disposed on a p+ drain region. The end portion has an inclined surface where the second insulating film thickness is reduced from the p+ drain region toward the channel region. A gate electrode is disposed on the channel region, the p+ source region, the p+ drain region, and the inclined surfaces of the first and the second insulating films through a gate insulating film including an aluminum oxide film.

Abstract: There is provided a semiconductor device that improves reliability. The impurity concentrations of a p|| source region and a p|| drain region are 5×1020 cm?3 or more. The channel-region-side end portion of a first insulating film is disposed on a p+ source region. The end portion has an inclined surface where the first insulating film thickness is reduced from the p? source region toward a channel region. The channel-region-side end portion of a second insulating film is disposed on a p+ drain region. The end portion has an inclined surface where the second insulating film thickness is reduced from the p+ drain region toward the channel region. A gate electrode is disposed on the channel region, the p+ source region, the p+ drain region, and the inclined surfaces of the first and the second insulating films through a gate insulating film including an aluminum oxide film.

Abstract: The present invention provides a switching device (100) for power conversion in which a first gate electrode (6), a p-type channel layer (2) having an n-type emitter region (3), a second gate electrode (13), and a p-type floating layer (15) are repeatedly arranged in order on the surface side of an n?type semiconductor substrate (1). An interval a between the two gates (6, 13) that sandwich the p-type channel layer (2) is configured to be smaller than an interval b between the two gates (13, 6) that sandwich the p-type floating layer (15). The first gate electrode (6) and the second gate electrode (13) are both supplied with drive signals having a time difference in drive timing.

Abstract: The present invention provides a switching device (100) for power conversion in which a first gate electrode (6), a p-type channel layer (2) having an n-type emitter region (3), a second gate electrode (13), and a p-type floating layer (15) are repeatedly arranged in order on the surface side of an n-type semiconductor substrate (1). An interval a between the two gates (6, 13) that sandwich the p-type channel layer (2) is configured to be smaller than an interval b between the two gates (13, 6) that sandwich the p-type floating layer (15). The first gate electrode (6) and the second gate electrode (13) are both supplied with drive signals having a time difference in drive timing.

Abstract: There is provided a semiconductor device including a first emitter layer of a first conductivity type, a drift layer of a second conductivity type, adjacent to the first emitter layer, a channel layer of the first conductivity type, adjacent to the drift layer, a second emitter layer of the second conductivity type, adjacent to the channel layer, a collector electrode electrically coupled to the first emitter layer, an emitter electrode electrically coupled to the second emitter layer, a first trench-gate electrode for controlling on and off of an electric current flowing between the collector electrode and the emitter electrode, and a second trench-gate electrode for controlling a turn-off power loss. The semiconductor device further includes a thyristor unit made up of the first emitter layer, the drift layer, the channel layer, and the second emitter layer.

Abstract: The present invention provides a switching device (100) for power conversion in which a first gate electrode (6), a p-type channel layer (2) having an n-type emitter region (3), a second gate electrode (13), and a p-type floating layer (15) are repeatedly arranged in order on the surface side of an n-type semiconductor substrate (1). An interval a between the two gates (6, 13) that sandwich the p-type channel layer (2) is configured to be smaller than an interval b between the two gates (13, 6) that sandwich the p-type floating layer (15). The first gate electrode (6) and the second gate electrode (13) are both supplied with drive signals having a time difference in drive timing.

Abstract: There is provided a semiconductor device including a first emitter layer of a first conductivity type, a drift layer of a second conductivity type, adjacent to the first emitter layer, a channel layer of the first conductivity type, adjacent to the drift layer, a second emitter layer of the second conductivity type, adjacent to the channel layer, a collector electrode electrically coupled to the first emitter layer, an emitter electrode electrically coupled to the second emitter layer, a first trench-gate electrode for controlling on and off of an electric current flowing between the collector electrode and the emitter electrode, and a second trench-gate electrode for controlling a turn-off power loss. The semiconductor device further includes a thyristor unit made up of the first emitter layer, the drift layer, the channel layer, and the second emitter layer.