Patents by Inventor Masahiro MASUNAGA

Masahiro MASUNAGA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11380764
    Abstract: The purpose of the present invention is to provide a semiconductor device comprising an epitaxial layer formed on a SiC substrate, and a CMOS formed in the top part of the epitaxial layer, wherein growth of any defects present at the interface between the SiC substrate and the epitaxial layer is suppressed, and the reliability of the semiconductor device is improved. As a means to achieve the foregoing, a semiconductor device is formed such that the distance from a p-type diffusion layer to the interface between an n-type epitaxial layer and an n-type semiconductor substrate is larger than the thickness of a depletion layer that extends from the p-type diffusion layer to the back side of the n-type semiconductor substrate in response to the potential difference between a substrate electrode and another substrate electrode.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: July 5, 2022
    Assignee: HITACHI, LTD.
    Inventors: Masahiro Masunaga, Shintaroh Sato, Akio Shima, Digh Hisamoto
  • Patent number: 11349000
    Abstract: An n type semiconductor layer is formed over an n type semiconductor substrate made of silicon carbide, a p type impurity region is formed in the semiconductor layer, and an n type drain region and an n type source region are formed in the impurity region. A field insulating film having an opening that selectively opens a part of the impurity region located between the drain and source regions is formed over the impurity region and the drain and source regions. A gate insulating film is formed over the impurity region in the opening, and a gate electrode is formed on the gate insulating film. Here, a field relaxation layer having an impurity concentration higher than that of the impurity region is formed in at least a part of the impurity region located between the drain and source regions in plan view and located below the field insulating film.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: May 31, 2022
    Assignee: HITACHI, LTD.
    Inventors: Masahiro Masunaga, Shintaroh Sato, Akio Shima, Ryo Kuwana, Isao Hara
  • Publication number: 20220149035
    Abstract: A semiconductor device includes an electrostatic protection circuit 1 and a MOSFET 2 including a gate terminal. The electrostatic protection circuit 1 includes a positive-side power supply terminal 3, a negative-side power supply terminal 5, a first protection diode 4, a second protection diode 6, a resistance element 7, and a bipolar transistor 8. The second protection diode 6 includes an anode terminal electrically connected to the negative-side power supply terminal 5 via the resistance element 7, and a cathode terminal electrically connected to the gate terminal. The bipolar transistor 8 includes a base terminal, an emitter terminal, and a collector terminal. The bipolar transistor 8 is electrically connected to the anode terminal of the second protection diode 6, the gate terminal, and the positive-side power supply terminal 3. The electrostatic protection circuit 1 is formed on a semiconductor substrate made of silicon carbide.
    Type: Application
    Filed: October 8, 2021
    Publication date: May 12, 2022
    Inventors: Masahiro Masunaga, Shinji Nomoto, Ryo Kuwana, Isao Hara
  • Patent number: 11239314
    Abstract: A MOSFET that has a drain region and a source region on an upper surface of a semiconductor substrate and a gate electrode that is formed on the semiconductor substrate, and an element separation insulating film that includes an opening portion which exposes an active region, on the semiconductor substrate, are formed. At this point, a gate leading-out interconnection that overlaps the element separation insulating film when viewed from above, and that is integrally combined with the gate electrode is formed in a position where the gate leading-out interconnection does not extend over a distance between both the drain region and the source region when viewed from above, on a region that is exposed from the gate electrode.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: February 1, 2022
    Assignee: HITACHI, LTD.
    Inventors: Masahiro Masunaga, Akio Shima, Shintaroh Sato, Ryo Kuwana
  • Publication number: 20210050348
    Abstract: Provided is a SiC semiconductor element equipped with a SiC integrated circuit having a stable characteristic, which operates normally even in a radiation environment. A radiation resistant circuit device includes: a SiC semiconductor element equipped with a SiC integrated circuit, a printed board on which the SiC semiconductor element is provided, a conductive wiring that is arranged inside the printed board and has a predetermined surface facing a bottom surface of a substrate electrode of the SiC integrated circuit, and an insulating material arranged between the bottom surface of the substrate electrode of the SiC integrated circuit and the predetermined surface of the conductive wiring.
    Type: Application
    Filed: July 23, 2020
    Publication date: February 18, 2021
    Inventors: Ryo KUWANA, Masahiro MASUNAGA, Mutsumi SUZUKI, Isao HARA
  • Publication number: 20200303505
    Abstract: An n type semiconductor layer is formed over an n type semiconductor substrate made of silicon carbide, a p type impurity region is formed in the semiconductor layer, and an n type drain region and an n type source region are formed in the impurity region. A field insulating film having an opening that selectively opens a part of the impurity region located between the drain and source regions is formed over the impurity region and the drain and source regions. A gate insulating film is formed over the impurity region in the opening, and a gate electrode is formed on the gate insulating film. Here, a field relaxation layer having an impurity concentration higher than that of the impurity region is formed in at least a part of the impurity region located between the drain and source regions in plan view and located below the field insulating film.
    Type: Application
    Filed: November 4, 2019
    Publication date: September 24, 2020
    Applicant: Hitachi, Ltd.
    Inventors: Masahiro MASUNAGA, Shintaroh SATO, Akio SHIMA, Ryo KUWANA, Isao HARA
  • Publication number: 20190326393
    Abstract: A MOSFET that has a drain region and a source region on an upper surface of a semiconductor substrate and a gate electrode that is formed on the semiconductor substrate, and an element separation insulating film that includes an opening portion which exposes an active region, on the semiconductor substrate, are formed. At this point, a gate leading-out interconnection that overlaps the element separation insulating film when viewed from above, and that is integrally combined with the gate electrode is formed in a position where the gate leading-out interconnection does not extend over a distance between both the drain region and the source region when viewed from above, on a region that is exposed from the gate electrode.
    Type: Application
    Filed: February 1, 2019
    Publication date: October 24, 2019
    Applicant: HITACHI, LTD.
    Inventors: Masahiro MASUNAGA, Akio SHIMA, Shintaroh SATO, Ryo KUWANA
  • Publication number: 20190319103
    Abstract: The purpose of the present invention is to provide a semiconductor device comprising an epitaxial layer formed on a SiC substrate, and a CMOS formed in the top part of the epitaxial layer, wherein growth of any defects present at the interface between the SiC substrate and the epitaxial layer is suppressed, and the reliability of the semiconductor device is improved. As a means to achieve the foregoing, a semiconductor device is formed such that the distance from a p-type diffusion layer to the interface between an n-type epitaxial layer and an n-type semiconductor substrate is larger than the thickness of a depletion layer that extends from the p-type diffusion layer to the back side of the n-type semiconductor substrate in response to the potential difference between a substrate electrode and another substrate electrode.
    Type: Application
    Filed: October 24, 2017
    Publication date: October 17, 2019
    Inventors: Masahiro MASUNAGA, Shintaroh SATO, Akio SHIMA, Digh HISAMOTO
  • Patent number: 10332997
    Abstract: There is provided a semiconductor device that improves reliability. The impurity concentrations of a p++ source region and a p++ drain region are 5×1020 cm?3 or more. The channel-region-side end portion of a first insulating film is disposed on a p+ source region. The end portion has an inclined surface where the first insulating film thickness is reduced from the p+ source region toward a channel region. The channel-region-side end portion of a second insulating film is disposed on a p+ drain region. The end portion has an inclined surface where the second insulating film thickness is reduced from the p+ drain region toward the channel region. A gate electrode is disposed on the channel region, the p+ source region, the p+ drain region, and the inclined surfaces of the first and the second insulating films through a gate insulating film including an aluminum oxide film.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: June 25, 2019
    Assignee: HITACHI, LTD.
    Inventors: Shintaroh Sato, Masahiro Masunaga, Akio Shima
  • Publication number: 20190148546
    Abstract: There is provided a semiconductor device that improves reliability. The impurity concentrations of a p|| source region and a p|| drain region are 5×1020 cm?3 or more. The channel-region-side end portion of a first insulating film is disposed on a p+ source region. The end portion has an inclined surface where the first insulating film thickness is reduced from the p? source region toward a channel region. The channel-region-side end portion of a second insulating film is disposed on a p+ drain region. The end portion has an inclined surface where the second insulating film thickness is reduced from the p+ drain region toward the channel region. A gate electrode is disposed on the channel region, the p+ source region, the p+ drain region, and the inclined surfaces of the first and the second insulating films through a gate insulating film including an aluminum oxide film.
    Type: Application
    Filed: October 23, 2018
    Publication date: May 16, 2019
    Inventors: Shintaroh SATO, Masahiro MASUNAGA, Akio SHIMA
  • Publication number: 20170141677
    Abstract: The present invention provides a switching device (100) for power conversion in which a first gate electrode (6), a p-type channel layer (2) having an n-type emitter region (3), a second gate electrode (13), and a p-type floating layer (15) are repeatedly arranged in order on the surface side of an n?type semiconductor substrate (1). An interval a between the two gates (6, 13) that sandwich the p-type channel layer (2) is configured to be smaller than an interval b between the two gates (13, 6) that sandwich the p-type floating layer (15). The first gate electrode (6) and the second gate electrode (13) are both supplied with drive signals having a time difference in drive timing.
    Type: Application
    Filed: January 31, 2017
    Publication date: May 18, 2017
    Inventors: Takayuki HASHIMOTO, Mutsuhiro MORI, Masahiro MASUNAGA
  • Patent number: 9595602
    Abstract: The present invention provides a switching device (100) for power conversion in which a first gate electrode (6), a p-type channel layer (2) having an n-type emitter region (3), a second gate electrode (13), and a p-type floating layer (15) are repeatedly arranged in order on the surface side of an n-type semiconductor substrate (1). An interval a between the two gates (6, 13) that sandwich the p-type channel layer (2) is configured to be smaller than an interval b between the two gates (13, 6) that sandwich the p-type floating layer (15). The first gate electrode (6) and the second gate electrode (13) are both supplied with drive signals having a time difference in drive timing.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: March 14, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Hashimoto, Mutsuhiro Mori, Masahiro Masunaga
  • Patent number: 9306047
    Abstract: There is provided a semiconductor device including a first emitter layer of a first conductivity type, a drift layer of a second conductivity type, adjacent to the first emitter layer, a channel layer of the first conductivity type, adjacent to the drift layer, a second emitter layer of the second conductivity type, adjacent to the channel layer, a collector electrode electrically coupled to the first emitter layer, an emitter electrode electrically coupled to the second emitter layer, a first trench-gate electrode for controlling on and off of an electric current flowing between the collector electrode and the emitter electrode, and a second trench-gate electrode for controlling a turn-off power loss. The semiconductor device further includes a thyristor unit made up of the first emitter layer, the drift layer, the channel layer, and the second emitter layer.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: April 5, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Hashimoto, Mutsuhiro Mori, Masahiro Masunaga
  • Publication number: 20150303288
    Abstract: The present invention provides a switching device (100) for power conversion in which a first gate electrode (6), a p-type channel layer (2) having an n-type emitter region (3), a second gate electrode (13), and a p-type floating layer (15) are repeatedly arranged in order on the surface side of an n-type semiconductor substrate (1). An interval a between the two gates (6, 13) that sandwich the p-type channel layer (2) is configured to be smaller than an interval b between the two gates (13, 6) that sandwich the p-type floating layer (15). The first gate electrode (6) and the second gate electrode (13) are both supplied with drive signals having a time difference in drive timing.
    Type: Application
    Filed: September 7, 2012
    Publication date: October 22, 2015
    Applicant: Hitachi, Ltd.
    Inventors: Takayuki HASHIMOTO, Mutsuhiro MORI, Masahiro MASUNAGA
  • Publication number: 20150279979
    Abstract: There is provided a semiconductor device including a first emitter layer of a first conductivity type, a drift layer of a second conductivity type, adjacent to the first emitter layer, a channel layer of the first conductivity type, adjacent to the drift layer, a second emitter layer of the second conductivity type, adjacent to the channel layer, a collector electrode electrically coupled to the first emitter layer, an emitter electrode electrically coupled to the second emitter layer, a first trench-gate electrode for controlling on and off of an electric current flowing between the collector electrode and the emitter electrode, and a second trench-gate electrode for controlling a turn-off power loss. The semiconductor device further includes a thyristor unit made up of the first emitter layer, the drift layer, the channel layer, and the second emitter layer.
    Type: Application
    Filed: October 5, 2012
    Publication date: October 1, 2015
    Inventors: Takayuki Hashimoto, Mutsuhiro Mori, Masahiro Masunaga
  • Publication number: 20150162429
    Abstract: A semiconductor device (10) includes an n-type drift layer (11) that is a semiconductor substrate; a p-type region (12) and an n-type region (13) that are formed on a surface of the semiconductor substrate and serving as anode regions; a high-concentration n-type region (15) formed on a back surface of the semiconductor substrate and serving as a cathode region; and an anode electrode (1). The semiconductor substrate includes, on its surface, a structure in which the p-type region (12) and the n-type region (13) are adjacent to each other, wherein the p-type region (12) is connected to the anode electrode (1), and the n-type region (13) is connected to the anode electrode (1) via a switch (14). A control unit (40) is connected to a control terminal of the switch (14). In a conduction state of the semiconductor device (10), the control unit (40) outputs a high-frequency pulse to the control terminal of the switch (14) to turn on and off the switch (14).
    Type: Application
    Filed: January 26, 2012
    Publication date: June 11, 2015
    Applicant: Hitachi, Ltd.
    Inventors: Takayuki Hashimoto, Masahiro Masunaga
  • Patent number: 8643102
    Abstract: A control device of a semiconductor device is provided. The control device of a semiconductor device is capable of reducing both ON resistance and feedback capacitance in a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided. In the control device controlling driving of a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided, a signal of tuning ON or OFF is outputted to a gate electrode in a state of outputting a signal of turning OFF to the second gate electrode.
    Type: Grant
    Filed: September 10, 2011
    Date of Patent: February 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takayuki Hashimoto, Masahiro Masunaga
  • Publication number: 20120217577
    Abstract: A trench-gate vertical-channel type power MOSFET has an advantage of a low on-state resistance. With increasing miniaturization, fluctuations in on-state resistance have posed a problem. In addition, a structural limitation in miniaturization also has posed a problem. These problems are not only those of a single power MOSFET but also are important ones in integrated circuit devices, such as IGBT using a similar structure, obtained by integrating CMOS and such a power active device on a single chip. The invention provides a semiconductor device having a trench-gate vertical-channel type power active device, such as trench-gate vertical-channel type power MOSFET, in which the width of the interlayer insulating film is made almost equal to that of the trench and a portion of the source region is comprised of a polysilicon member.
    Type: Application
    Filed: February 23, 2012
    Publication date: August 30, 2012
    Inventors: Takayuki HASHIMOTO, Masahiro Masunaga
  • Publication number: 20120061722
    Abstract: A control device of a semiconductor device is provided. The control device of a semiconductor device is capable of reducing both ON resistance and feedback capacitance in a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided. In the control device controlling driving of a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided, a signal of tuning ON or OFF is outputted to a gate electrode in a state of outputting a signal of turning OFF to the second gate electrode.
    Type: Application
    Filed: September 10, 2011
    Publication date: March 15, 2012
    Inventors: Takayuki HASHIMOTO, Masahiro Masunaga
  • Publication number: 20110241644
    Abstract: Technology of reducing leakage current in a planar MOSFET and a hollow gate type planar MOSFET is provided. In a planar MOSFET (and hollow gate type planar MOSFET), regions close to a channel in n-type source regions have a shallow depth (shallow n-type source region), and regions away from the channel have a large depth (deep n-type source region). Protruding portions in a horizontal direction of p-type well regions are positioned further inside than a surface of a substrate. In this manner, a planar MOSFET (and a hollow gate type planar MOSFET) having small leakage current can be achieved, and thus there is an effect in loss reduction in a power source using the planar MOSFET (and the hollow gate type planar MOSFET).
    Type: Application
    Filed: March 29, 2011
    Publication date: October 6, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Takayuki HASHIMOTO, Masahiro MASUNAGA