Patents by Inventor Masahiro Miyairi

Masahiro Miyairi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10852648
    Abstract: According to one embodiment, a mask pattern correction system includes the following configuration. A stress analysis circuitry divides a layout of a circuit pattern formed using a design mask formed in accordance with mask design data into correction regions, and acquires a displacement amount from the regions. A correction value calculation circuitry calculates a displacement correction value from the displacement amount. A correction map generation circuitry generates a correction map based on a correction value difference of the displacement correction values. A mask position correction circuitry allocates the regions to a layout of the circuit pattern, performs displacement correction of a mask pattern on the design mask by the displacement correction values, and creates a correction mask based on the displacement correction.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: December 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuyuki Hino, Hiromitsu Mashita, Masahiro Miyairi, Hiroshi Yoshimura, Taiga Uno, Sachiyo Ito, Shinichirou Ooki, Kenji Shiraishi, Hirotaka Ichikawa, Yuto Takeuchi
  • Publication number: 20200117104
    Abstract: According to one embodiment, a mask pattern correction system includes the following configuration. A stress analysis circuitry divides a layout of a circuit pattern formed using a design mask formed in accordance with mask design data into correction regions, and acquires a displacement amount from the regions. A correction value calculation circuitry calculates a displacement correction value from the displacement amount. A correction map generation circuitry generates a correction map based on a correction value difference of the displacement correction values. A mask position correction circuitry allocates the regions to a layout of the circuit pattern, performs displacement correction of a mask pattern on the design mask by the displacement correction values, and creates a correction mask based on the displacement correction.
    Type: Application
    Filed: September 10, 2019
    Publication date: April 16, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuyuki HINO, Hiromitsu MASHITA, Masahiro MIYAIRI, Hiroshi YOSHIMURA, Taiga UNO, Sachiyo ITO, Shinichirou OOKI, Kenji SHIRAISHI, Hirotaka ICHIKAWA, Yuto TAKEUCHI
  • Patent number: 10151972
    Abstract: A manufacturing method of a photomask according to the embodiment sets an exposure condition applied when a resist is formed into a three-dimensional target shape by using a photomask including a plurality of light-shielding areas. Subsequently, the method sets a hypothetical target shape obtained by correcting a target shape based on a development characteristic of the resist for the exposure condition. Subsequently, the method creates a pattern of the photomask corresponding to the hypothetical target shape. Subsequently, the method simulates a prediction shape of the resist when the pattern is used. Subsequently, the method calculates a cost function related to an error between the prediction shape and the hypothetical target shape. Subsequently, the method adjusts the pattern based on a result of the calculation of the cost function.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: December 11, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takaki Hashimoto, Satoshi Usui, Naoki Sato, Kouichi Nakayama, Masahiro Miyairi, Syogo Okamoto
  • Publication number: 20180157167
    Abstract: A manufacturing method of a photomask according to the embodiment sets an exposure condition applied when a resist is formed into a three-dimensional target shape by using a photomask including a plurality of light-shielding areas. Subsequently, the method sets a hypothetical target shape obtained by correcting a target shape based on a development characteristic of the resist for the exposure condition. Subsequently, the method creates a pattern of the photomask corresponding to the hypothetical target shape. Subsequently, the method simulates a prediction shape of the resist when the pattern is used. Subsequently, the method calculates a cost function related to an error between the prediction shape and the hypothetical target shape. Subsequently, the method adjusts the pattern based on a result of the calculation of the cost function.
    Type: Application
    Filed: March 1, 2017
    Publication date: June 7, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takaki HASHIMOTO, Satoshi Usui, Naoki Sato, Kouichi Nakayama, Masahiro Miyairi, Syogo Okamoto
  • Patent number: 9268208
    Abstract: One embodiment includes: a step of evaluating an amount of flare occurring through a mask at EUV exposure; a step of providing a dummy mask pattern on the mask based on the evaluated result of the amount of flare; and a step of executing a flare correction and an optical proximity correction on a layout pattern. The layout pattern is provided by the EUV exposure through the mask with the dummy mask pattern.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: February 23, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Aburada, Hiromitsu Mashita, Taiga Uno, Masahiro Miyairi, Toshiya Kotani
  • Publication number: 20130063707
    Abstract: One embodiment includes: a step of evaluating an amount of flare occurring through a mask at EUV exposure; a step of providing a dummy mask pattern on the mask based on the evaluated result of the amount of flare; and a step of executing a flare correction and an optical proximity correction on a layout pattern. The layout pattern is provided by the EUV exposure through the mask with the dummy mask pattern.
    Type: Application
    Filed: March 15, 2012
    Publication date: March 14, 2013
    Inventors: Ryota ABURADA, Hiromitsu Mashita, Taiga Uno, Masahiro Miyairi, Toshiya Kotani
  • Patent number: 8336004
    Abstract: According to a mask verifying method of the embodiment, a difference between an actual dimension of a mask pattern and a simulation dimension is calculated as a computational estimated value. Moreover, a difference between an actual dimension of the mask pattern that is actually measured and a dimension on pattern data is calculated as an actually-measured difference. Then, it is verified whether a mask pattern dimension passes or fails based on the calculated value. When calculating the computational estimated value, a model function, which is set based on each correspondence relationship between an actual dimension and a mask simulation dimension of a test pattern, which includes a plurality of types of pattern ambient environments, to the mask pattern.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: December 18, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Nojima, Tetsuaki Matsunawa, Shigeru Hasebe, Masahiro Miyairi
  • Patent number: 8261214
    Abstract: A graph in which patterns are each regarded as nodes and nodes of patterns adjacent to each other at a first distance are connected with each other by an edge is produced, each of the patterns is classified into two types so that the two patterns corresponding to the nodes at both ends of the edge are types different to each other, a classification result is corrected by grouping the patterns in each node cluster connected by the edge or each node cluster connected via the node by the edge, and by inverting each of types of a pattern belonging to a same group as that of one pattern, out of a pair of patterns that are classified into a same type and that belong to respectively different groups adjacent to each other at a second distance, and a pattern layout diagram is created based on the corrected classification result.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: September 4, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shimon Maeda, Masahiro Miyairi, Soichi Inoue
  • Patent number: 8234596
    Abstract: A pattern data creating method according to an embodiment of the present invention comprises: extracting marginal error patterns using a first result obtained by applying process simulation to mask pattern data based on an evaluation target cell pattern, applying the process simulation to mask pattern data based on an evaluation target cell pattern with peripheral environment pattern created by arranging a peripheral environment pattern in the marginal error patterns such that a second result obtained by creating mask pattern data and applying the process simulation to the mask pattern data is more deteriorated than the first result, and correcting the evaluation target cell pattern or the mask pattern data based on the evaluation target cell pattern when there is a fatal error.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: July 31, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryuji Ogawa, Masahiro Miyairi, Shimon Maeda, Suigen Kyoh, Satoshi Tanaka
  • Publication number: 20120054697
    Abstract: According to one embodiment, a light source shape calculation method includes calculating a first light source shape as an exposure illumination light source shape, so that the first light source shape has a light source shape region symmetrical to an X-axis direction and a Y-axis direction, and a process margin when forming an on-substrate pattern corresponding to at least two pattern layouts defined by design rules is optimized. A point light source is calculated such that the process margin of formation of the on-substrate pattern corresponding to a pattern layout to be formed on a semiconductor device is optimized, and is applied to the first light source shape.
    Type: Application
    Filed: August 31, 2011
    Publication date: March 1, 2012
    Inventors: Kazuhiro TAKAHATA, Tetsuaki MATSUNAWA, Masahiro MIYAIRI, Shimon MAEDA, Shigeki NOJIMA
  • Publication number: 20110201138
    Abstract: According to a mask verifying method of the embodiment, a difference between an actual dimension of a mask pattern and a simulation dimension is calculated as a computational estimated value. Moreover, a difference between an actual dimension of the mask pattern that is actually measured and a dimension on pattern data is calculated as an actually-measured difference. Then, it is verified whether a mask pattern dimension passes or fails based on the calculated value. When calculating the computational estimated value, a model function, which is set based on each correspondence relationship between an actual dimension and a mask simulation dimension of a test pattern, which includes a plurality of types of pattern ambient environments, to the mask pattern.
    Type: Application
    Filed: February 10, 2011
    Publication date: August 18, 2011
    Inventors: Shigeki Nojima, Tetsuaki Matsunawa, Shigeru Hasebe, Masahiro Miyairi
  • Publication number: 20110029938
    Abstract: According to one embodiment, a pattern creating method includes: calculating, from pattern data on which a circuit pattern formed on a substrate and an auxiliary pattern not formed on the substrate are arranged, a first feature value of a first pattern edge of a circuit pattern affected by the auxiliary pattern and a second feature value of a second pattern edge connected to the first pattern edge; and arranging, when a relation between the feature values does not have a desired relation corresponding to the circuit pattern, the auxiliary pattern such that the relation between the feature values has the relation corresponding to a shape of the circuit pattern.
    Type: Application
    Filed: July 26, 2010
    Publication date: February 3, 2011
    Inventors: Shigeki NOJIMA, Masahiro MIYAIRI
  • Publication number: 20100191357
    Abstract: A graph in which patterns are each regarded as nodes and nodes of patterns adjacent to each other at a first distance are connected with each other by an edge is produced, each of the patterns is classified into two types so that the two patterns corresponding to the nodes at both ends of the edge are types different to each other, a classification result is corrected by grouping the patterns in each node cluster connected by the edge or each node cluster connected via the node by the edge, and by inverting each of types of a pattern belonging to a same group as that of one pattern, out of a pair of patterns that are classified into a same type and that belong to respectively different groups adjacent to each other at a second distance, and a pattern layout diagram is created based on the corrected classification result.
    Type: Application
    Filed: December 3, 2009
    Publication date: July 29, 2010
    Inventors: Shimon Maeda, Masahiro Miyairi, Soichi Inoue
  • Publication number: 20100081294
    Abstract: A pattern data creating method according to an embodiment of the present invention comprises: extracting marginal error patterns using a first result obtained by applying process simulation to mask pattern data based on an evaluation target cell pattern, applying the process simulation to mask pattern data based on an evaluation target cell pattern with peripheral environment pattern created by arranging a peripheral environment pattern in the marginal error patterns such that a second result obtained by creating mask pattern data and applying the process simulation to the mask pattern data is more deteriorated than the first result, and correcting the evaluation target cell pattern or the mask pattern data based on the evaluation target cell pattern when there is a fatal error.
    Type: Application
    Filed: September 1, 2009
    Publication date: April 1, 2010
    Inventors: Ryuji OGAWA, Masahiro Miyairi, Shimon Maeda, Suigen Kyoh, Satoshi Tanaka