Patents by Inventor Masahiro Murakawa

Masahiro Murakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100020671
    Abstract: The present invention provides a phase correction element which can be used for recording and/or reproducing an information of three types of optical disks for HD, DVD and CD by employing a single objective lens for HD, and an optical head device.
    Type: Application
    Filed: January 31, 2005
    Publication date: January 28, 2010
    Applicant: ASAHI GLASS COMPANY LIMITED
    Inventors: Yoshiharu Ooi, Masahiro Murakawa, Hiromasa Sato, Masao Miyamura
  • Patent number: 7636706
    Abstract: A parameter adjusting device configured to adjust a great number of parameters of a physical model by a genetic algorithm using multiple processing units within a short time. A parameter adjusting device comprises a processing assignment means wherein a part of a multiple processing means is assigned to search processing by a local search method, and assigns the processing of the local search to a low-performance processor. Also, the parameter adjusting device collects an interim result of the search by a genetic algorithm, and uses it for the search processing by the local search method. Through parallelization and efficiency of an adjusting processing by effectively utilizing the resource in the system, the parameter adjusting device can determine the group of the most appropriate parameters within a short time.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: December 22, 2009
    Assignee: Evolvable Systems Research Institute Inc.
    Inventors: Masahiro Murakawa, Keiichi Ito
  • Patent number: 7583749
    Abstract: A transmitting circuit 10 converts transmission data to a multilevel analog signal suitable for transmission. The multilevel analog signal is output to a cable 21 via an amplifier and a hybrid circuit 12. In the transmitting circuit 10, a waveform which compensates waveform deterioration at the cable 21 is generated. A reception signal from the cable 21 is input to a mixer 14 via the hybrid circuit 12 and an amplifier 13. The mixer 14 mixes the reception signal and a cancel signal output from a cancel signal generation circuit 17 so as to remove undesired signals. In a receiving circuit 15, the signal output from the mixer 14 is sampled by use of a plurality of sample-hold circuits, and subjected to analog sum-of-product computation which is performed by a matrix circuit for distortion compensation. Subsequently, the sampled signals are converted to digital signals.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: September 1, 2009
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Yuji Kasai, Masahiro Murakawa, Tetsuya Higuchi
  • Patent number: 7580904
    Abstract: A chromosome using each of a plurality of parameters of a physical model of a semiconductor element as a gene is defined and the parameters are optimized using a genetic algorithm based on the characteristics measurement data of the semiconductor element fabricated by way of trial. In the selection processing of the genetic algorithm, a sum of a first evaluation value based on linear scale data and a second evaluation value based on logarithmic scale data is employed as the evaluation value of the chromosome.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: August 25, 2009
    Assignee: Evolvable Systems Research Institute Inc.
    Inventors: Masahiro Murakawa, Keiichi Ito, Tetsunori Wada
  • Patent number: 7564504
    Abstract: A phase plate having a reduced size and a reduced weight and having accurately parted regions while it has the same function as a conventional two-parted optical rotation plate and an optical data recording/reproducing device capable of stably recording and reproducing are presented. A phase plate P1 comprising a polymer liquid crystal film 2 held between transparent substrates i, 4, wherein the polymer liquid crystal film 2 is parted spatially in the region into which an incident light enters, so that the light transmitting the phase plate assumes a different state of polarization depending on an aligning direction of the molecules of the polymer liquid crystal film 2. The phase plate is located as a two-parted optical rotation plate in an optical data recording/reproducing device.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: July 21, 2009
    Assignee: Asahi Glass Company, Limited
    Inventors: Yoshiharu Ooi, Ryota Murakami, Hiromasa Sato, Takuji Nomura, Masahiro Murakawa, Yoshiyuki Miyake
  • Publication number: 20090138417
    Abstract: Efficient and high-accuracy parameter adjustment is performed by applying a genetic algorithm to a parameter adjustment such as a physical model of a transistor and so on. A parameter adjusting device includes a device generating new parameter genes by an initial population generating device and a special crossover processing by a Latin hyper square method. Also, a normalization device is provided for applying to parameters which are real numbers. Moreover, for example, to exactly meet a specific property of the transistor (MOSFET), an evaluation device which evaluates a parameter in consideration of a log scale, is provided. According to the above-mentioned structure, the genetic algorithm can be applied to the parameter adjustment with a large number of parameters such as the physical model of the transistor and so on, so that a parameter group can be determined with a high degree of accuracy within a short time.
    Type: Application
    Filed: April 3, 2006
    Publication date: May 28, 2009
    Applicant: Evolvable Systems Research
    Inventors: Masahiro Murakawa, Keiichi Ito, Shunsuke Baba
  • Patent number: 7533356
    Abstract: A parameter adjusting device and a parameter adjusting method configured to adjust a great number of parameters used for a circuit design model of a semiconductor element such as a transistor within a short time. A parameter adjusting device adapts a circuit design model wherein a formula for analysis is derived based on a surface potential such as, for example, the HiSIM, as the circuit design model of a semiconductor element; defines a chromosome wherein a respective great number of parameters of the model are genes; and optimizes the parameter based on property measured data of a tested element, using a genetic algorithm. Parameter adjustment comprises a first step adjusting the parameters which determine the structure of the semiconductor element based on the property measured data of a long channel group; and a second step adjusting nonadjusted parameters based on the property measured data of various lengths of channels with reference to a result of the first step.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: May 12, 2009
    Assignee: Evolvable Systems Research Institute Inc.
    Inventors: Masahiro Murakawa, Keiichi Ito, Michiko Miura
  • Publication number: 20090044275
    Abstract: It is an object of the present invention to realize a network system which can quickly detect a virus and tends not to be a new cause of vulnerability. A packet data comparator disclosed by the present invention branches inputted packet data into three branches, and includes an additional pattern matching unit which compares the branched packet data with a part of stored data and performs matching with collation patterns stored in a rewritable storage area, a fixed pattern matching unit which compares the branched packet data with the part of the stored data and performs the matching with a logical operation which has been configured with known collation patterns, a notification packet matching unit which compares the branched packet data with the part of the stored data and finds a notification packet, and an identity detection aggregation unit which aggregates results from the respective matching units.
    Type: Application
    Filed: March 26, 2008
    Publication date: February 12, 2009
    Applicant: National Institute of Adv. Ind. Science and Tech.
    Inventors: Eiichi TAKAHASHI, Masahiro YASUDA, Yosuke IIJIMA, Masahiro MURAKAWA, Kenji TODA, Tetsuya HIGUCHI
  • Publication number: 20080281986
    Abstract: A parameter adjusting device optimizes parameters using a genetic algorithm by using a plurality of processing devices. The plurality of processing devices is respectively configured to individually and simultaneously execute the genetic algorithm and to, a predetermined period prior each local search, be such that each processing device, in accordance with the genetic algorithm processing, based on predetermined numbers, send individuals of a genetic population to others of the plurality of processing devices and further configured to have a migration arrangement for receiving the predetermined numbers.
    Type: Application
    Filed: July 17, 2008
    Publication date: November 13, 2008
    Applicant: EVOLVABLE SYSTEMS RESEARCH INSTITUTE INC.
    Inventors: Masahiro Murakawa, Keiichi Ito
  • Publication number: 20080276215
    Abstract: A method for designing a mask pattern realizes shortening the ever-growing time for the OPC treatment, decreases the fabrication TAT of a semiconductor device and cuts cost. A method for fabricating a semiconductor device uses the mask pattern designed. This invention performs the OPC treatment in advance on a cell library constituting the basic configuration of a semiconductor circuit pattern and prepares a semiconductor chip using the cell library that has undergone the OPC treatment.
    Type: Application
    Filed: March 28, 2006
    Publication date: November 6, 2008
    Applicants: National Inst. of Adv. Indust. Science and Tech., Runesas Technology Corporation
    Inventors: Tetsuya Higuchi, Hirokazu Nosato, Masahiro Murakawa, Hidenori Sakanashi, Nobuyuki Yoshioka, Tsuneo Terasawa, Toshihiko Tanaka
  • Patent number: 7447289
    Abstract: Delay time between an input of data to a circuit block and an output of the data from the data block is measured in accordance with a timing at which the data from the circuit block is acquired by a measurement register and a timing at which the data from the circuit block is acquired by a data latch. An LSI tester sets well voltage adjustment values so that delay time of each circuit block is averaged. From voltages generated by the adjustment voltage generating circuit, a selector selects voltages that are in accordance with the well voltage adjustment values. The voltages selected are applied to a well of a CMOS transistor of each clock timing adjustment circuit. Delay time between timings of inputted clocks is thus adjusted.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: November 4, 2008
    Assignees: Sharp Kabushiki Kaisha, National Institute of Advanced Industrial Science and Technology
    Inventors: Munehiro Uratani, Eiichi Takahashi, Yuji Kasai, Tetsuya Higuchi, Masahiro Murakawa
  • Publication number: 20080250383
    Abstract: A mask pattern designing method capable of achieving the reduction in the increasing OPC processing time, shortening the manufacture TAT of a semiconductor device, and achieving the cost reduction is provided. An OPC (optical proximity correction) process at the time when a cell is singularly arranged is performed to a cell library pattern which forms a basic structure of a semiconductor circuit pattern in advance, and a semiconductor chip is produced using the cell library pattern to which the OPC process has been performed. At this time, since the cell library pattern which has been OPC-processed in advance is influenced by the cell library patterns around it, the correction process thereof is performed to the end portions of the patterns near the cell boundary. As particularly effective OPC correction means, the genetic algorithm is used.
    Type: Application
    Filed: September 26, 2006
    Publication date: October 9, 2008
    Inventors: Toshihiko Tanaka, Tsuneo Terasawa, Nobuyuki Yoshioka, Tetsuya Higuchi, Hidenori Sakanashi, Hirokazu Nosato, Masahiro Murakawa
  • Patent number: 7295032
    Abstract: A purpose of a high-speed signal transmission system of the present invention is to pass a high-speed digital signal through an outside-chip line exchanging a signal with a high speed LSI chip with a band higher than GHz. The high-speed signal transmission system of the present invention has a configuration of: insertion of a circuit for feeding back received information and adjusting a waveform at a sending side based on genetic algorithm; a device structure for automatically performing pump up and pump down of a transistor carrier; a transmission line of a wiring out of a transistor; and elimination of a common power source of a circuit.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: November 13, 2007
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Kanji Otsuka, Tamotsu Usami, Tetsuya Higuchi, Eiichi Takahashi, Yuji Kasai, Masahiro Murakawa
  • Publication number: 20070198103
    Abstract: A parameter adjusting device and a parameter adjusting method configured to adjust a great number of parameters used for a circuit design model of a semiconductor element such as a transistor within a short time. A parameter adjusting device adapts a circuit design model wherein a formula for analysis is derived based on a surface potential such as, for example, the HiSIM, as the circuit design model of a semiconductor element; defines a chromosome wherein a respective great number of parameters of the model are genes; and optimizes the parameter based on property measured data of a tested element, using a genetic algorithm. Parameter adjustment comprises a first step adjusting the parameters which determine the structure of the semiconductor element based on the property measured data of a long channel group; and a second step adjusting nonadjusted parameters based on the property measured data of various lengths of channels with reference to a result of the first step.
    Type: Application
    Filed: March 29, 2005
    Publication date: August 23, 2007
    Applicant: EVOLVABLE SYSTEMS RESEARCH INSTITUTE INC.
    Inventors: Masahiro Murakawa, Keiichi Ito, Michiko Miura
  • Patent number: 7259009
    Abstract: Disclosed are replicatable viral DNA vectors encoding a site-specific DNA-altering enzyme and a DNA target recognized by the enzyme, the enzyme selectively converting, in a cell expressing the enzyme, the DNA vector to a rearranged form. The invention further relates to methods for assembling recombinant adenoviral DNAs. These methods include the steps of: (a) providing a first linearized DNA vector including a restriction site and a cos site and a second linearized DNA vector including the restriction site, an adenoviral nucleic acid molecule, and a cos site; and (b) ligating the first and second linearized DNA vectors, the ligation assembling a recombinant adenoviral DNA.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: August 21, 2007
    Assignee: The General Hospital Corporation
    Inventors: Brian Seed, Mason Wright Freeman, Alexander Kovtun, Masahiro Murakawa, Eun-Chung Park, Xinzhong Wang
  • Publication number: 20070166286
    Abstract: Disclosed are replicatable viral DNA vectors encoding a site-specific DNA-altering enzyme and a DNA target recognized by the enzyme, the enzyme selectively converting, in a cell expressing the enzyme, the DNA vector to a rearranged form. The invention further relates to methods for assembling recombinant adenoviral DNAs. These methods include the steps of: (a) providing a first linearized DNA vector including a restriction site and a cos site and a second linearized DNA vector including the restriction site, an adenoviral nucleic acid molecule, and a cos site; and (b) ligating the first and second linearized DNA vectors, the ligation assembling a recombinant adenoviral DNA.
    Type: Application
    Filed: March 13, 2007
    Publication date: July 19, 2007
    Inventors: Brian Seed, Mason Freeman, Alexander Kovtun, Masahiro Murakawa, Eun-Chung Park, Xinzhong Wang
  • Publication number: 20070150435
    Abstract: A parameter adjusting device configured to adjust a great number of parameters of a physical model by a genetic algorithm using multiple processing units within a short time. A parameter adjusting device comprises a processing assignment means wherein a part of a multiple processing means is assigned to search processing by a local search method, and assigns the processing of the local search to a low-performance processor. Also, the parameter adjusting device collects an interim result of the search by a genetic algorithm, and uses it for the search processing by the local search method. Through parallelization and efficiency of an adjusting processing by effectively utilizing the resource in the system, the parameter adjusting device can determine the group of the most appropriate parameters within a short time.
    Type: Application
    Filed: December 22, 2004
    Publication date: June 28, 2007
    Applicant: EVOLVABLE SYSTEMS RESEARCH INSTITUTE INC.
    Inventors: Masahiro Murakawa, Keiichi Ito
  • Publication number: 20060242686
    Abstract: The present invention detects a computer virus at high speed from digital data acquired through a network using hardware in virus monitoring. With the invention, in an information processing terminal 002 capable of communicating with other information processing apparatus through a communication network 005, a virus checking apparatus 001 constructed of a hardware circuit is disposed in the side of an input channel of the network 005 and a virus is checked from input data from the network 005 by the virus checking apparatus 001. In order to change a virus pattern collated with the input data by hardware, the hardware circuit is detachably mounted or a rewritable logic device is used in the hardware circuit. The virus pattern of the logic device can be rewritten by sending virus definition information of a server 004 or control data generated based on this information to the virus checking apparatus 001.
    Type: Application
    Filed: February 20, 2004
    Publication date: October 26, 2006
    Inventors: Kenji Toda, Tetsuya Higuchi, Eiichi Takahashi, Masahiro Murakawa, Masaya Iwata
  • Publication number: 20060236146
    Abstract: A digital system (1) which performs a digital processing according to a single or a plurality of clock signals to deliver a specified basic function, and which comprises a plurality of delay elements (4) respectively inserted into a plurality of clock circuits for supplying clock signals in a digital system, and respectively constituted by circuit elements for changing delay times according to values indicated by a control signal, and a plurality of holding circuits (5) for holding a plurality of control signals to be given to a plurality of delay elements. The plurality of holding circuits have a plurality of control signal values, held by these holding circuits, changed by external devices (6-8) according to a probabilistic search method with the digital system (1) supplied with power from a variable-output-voltage power supply (14) so that the basic function of the digital system satisfies specified specifications.
    Type: Application
    Filed: June 3, 2004
    Publication date: October 19, 2006
    Applicant: National Inst of Adv Industrial Science and Tech
    Inventors: Eiichi Takahashi, Masahiro Murakawa, Yuji Kasai, Tetsuya Higuchi
  • Publication number: 20060158287
    Abstract: A chromosome using each of a plurality of parameters of a physical model of a semiconductor element as a gene is defined and the parameters are optimized using a genetic algorithm based on the characteristics measurement data of the semiconductor element fabricated by way of trial. In the selection processing of the genetic algorithm, a sum of a first evaluation value based on linear scale data and a second evaluation value based on logarithmic scale data is employed as the evaluation value of the chromosome.
    Type: Application
    Filed: July 15, 2004
    Publication date: July 20, 2006
    Applicant: Evolvable Systems Research
    Inventors: Masahiro Murakawa, Keiichi Ito, Tetsunori Wada