Patents by Inventor Masahiro Sekiguchi
Masahiro Sekiguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11659839Abstract: Provided is a component having plant defense activity. A PR1 gene expression activator containing a culture of a unicellular alga containing a green photosynthetic pigment as an active ingredient; A plant defense activator containing a culture of a unicellular alga containing a green photosynthetic pigment as an active ingredient; A plant disease preventive or ameliorating agent containing a culture of a unicellular alga containing a green photosynthetic pigment as an active ingredient; and a method of producing a plant defense activating component containing: cultivating a unicellular alga containing a green photosynthetic pigment under an aerobic condition to produce a culture containing an extracellular polysaccharide.Type: GrantFiled: March 22, 2019Date of Patent: May 30, 2023Assignees: PANAC CO., LTD., NATIONAL INSTITUTE OF TECHNOLOGY AND EVALUATIONInventors: Gouki Satou, Toshichika Ooki, Masahiro Koide, Hiroshi Sekiguchi
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Publication number: 20160276532Abstract: According to one embodiment, semiconductor light emitting element includes: a substrate having a first surface and a second surface on an opposite side of the first surface; an insulating layer provided on the second surface of the substrate; a first metal layer provided on the insulating layer; a semiconductor light emitting unit provided on the first metal layer, the semiconductor light emitting unit including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, the second semiconductor layer being electrically connected to the first metal layer; and a first electrode layer provided on the first surface of the substrate, the first electrode layer extending in the substrate and in the insulating layer, and the first electrode layer being electrically connected to the first metal layer.Type: ApplicationFiled: March 4, 2016Publication date: September 22, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Kentaro MORI, Takeyuki Suzuki, Mie Matsuo, Masahiro Sekiguchi, Koji Kaga
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Patent number: 8778778Abstract: According to an embodiment, an active layer is formed on a first surface of a semiconductor substrate, a wiring layer is formed on the active layer, and an insulating layer is formed covering the wiring layer. The first surface of the semiconductor substrate is bonded to a support substrate via the insulating layer, and the semiconductor substrate bonded to the support substrate is thinned leaving the semiconductor substrate having a predetermined thickness which covers the active layer from a second surface. At least a part of area of the thinned semiconductor substrate is removed to expose the active layer.Type: GrantFiled: August 18, 2011Date of Patent: July 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kazumasa Tanida, Masahiro Sekiguchi, Masayuki Dohi, Tsuyoshi Matsumura, Hideo Numata, Mari Otsuka, Naoko Yamaguchi, Takashi Shirono, Satoshi Hongo
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Patent number: 8580652Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate having first and second main surfaces, and a through hole passing through between the first and second main surfaces, a pad on the first main surface, a through electrode in the through hole, and a connection structure including a connection portion to directly connect the pad and the through electrode, and another connection portion to indirectly connect the pad and the through electrode. The method includes forming an isolation region in the first main surface, the isolation region being in a region where the through electrode is to be formed and being in a region other than the region where the through hole is to be formed, forming the pad, and forming the through hole by processing the substrate to expose a part of the pad.Type: GrantFiled: September 3, 2010Date of Patent: November 12, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Atsuko Kawasaki, Kenichiro Hagiwara, Ikuko Inoue, Kazutaka Akiyama, Itsuko Sakai, Mie Matsuo, Masahiro Sekiguchi, Yoshiteru Koseki, Hiroki Neko, Koushi Tozuka, Kazuhiko Nakadate, Takuto Inoue
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Patent number: 8338918Abstract: A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface of the semiconductor substrate opposite to a first main surface thereof facing to the supporting substrate to reduce a thickness of the semiconductor substrate to a predetermined thickness.Type: GrantFiled: June 20, 2011Date of Patent: December 25, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masahiro Sekiguchi, Eiji Takano, Tatsuhiko Shirakawa, Kenichiro Hagiwara, Masayuki Dohi, Susumu Harada
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Patent number: 8269315Abstract: A semiconductor device 1 has a through hole 3 formed in a second substrate 2. On the front surface of the semiconductor substrate 2, a first insulating layer 4 is coated having an opening 4a of the same diameter as that of the through hole 3, and a first wiring layer 5 is formed on the first insulating layer 4. Further, near the first wiring layer 5, the through hole 3 and a through connection portion constituted of a third insulating layer 8 formed on the inner surface and the like and a third wiring layer 9 filled and formed in the through hole 3 are formed. In addition, a second wiring layer 7 internally contacting the through connection portion is electrically connected with the first wiring layer 5. Between the inner surface of the through hole 3 and the first wiring layer 5, a second insulating layer 6 intervenes so that the first wiring layer 5 is separated from the third wiring layer 9 filled and formed in the through hole 3.Type: GrantFiled: June 6, 2008Date of Patent: September 18, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Kazumasa Tanida, Masahiro Sekiguchi, Kenji Takahashi
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Patent number: 8237285Abstract: Semiconductor device includes semiconductor substrate, through hole having first opening and second opening, and including an expansion portion so that an opening area of first opening is greater than an opening area of lowermost portion of expansion portion, first insulating layer, and having an opening which communicates with through hole and has an area smaller than opening area of first opening, first wiring layer provided on first insulating layer, second insulating layer provided on expansion portion of through hole, and to cover first opening and an inner wall surface of through hole, second insulating layer having an opening communicating with opening of first insulating layer so as to expose first wiring layer through opening of first insulating layer, and second wiring layer provided on second insulating layer to extend from inside of through hole, and being connected to first wiring layer via openings of first and second insulating layers.Type: GrantFiled: July 31, 2009Date of Patent: August 7, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Kazumasa Tanida, Mie Matsuo, Masahiro Sekiguchi, Chiaki Takubo
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Patent number: 8228426Abstract: A semiconductor package includes a solid-state imaging element, electrode pad, through-hole electrode, and light-transmitting substrate. The solid-state imaging element is formed on the first main surface of a semiconductor substrate. The electrode pad is formed on the first main surface of the semiconductor substrate. The through-hole electrode is formed to extend through the semiconductor substrate between the first main surface and a second main surface opposite to the electrode pad formed on the first main surface. The light-transmitting substrate is placed on a patterned adhesive to form a hollow on the solid-state imaging element. The thickness of the semiconductor substrate below the hollow when viewed from the light-transmitting substrate is larger than that of the semiconductor substrate below the adhesive.Type: GrantFiled: July 29, 2009Date of Patent: July 24, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Mie Matsuo, Atsuko Kawasaki, Kenji Takahashi, Masahiro Sekiguchi, Kazumasa Tanida
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Publication number: 20120049312Abstract: According to an embodiment, an active layer is formed on a first surface of a semiconductor substrate, a wiring layer is formed on the active layer, and an insulating layer is formed covering the wiring layer. The first surface of the semiconductor substrate is bonded to a support substrate via the insulating layer, and the semiconductor substrate bonded to the support substrate is thinned leaving the semiconductor substrate having a predetermined thickness which covers the active layer from a second surface. At least a part of area of the thinned semiconductor substrate is removed to expose the active layer.Type: ApplicationFiled: August 18, 2011Publication date: March 1, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazumasa TANIDA, Masahiro Sekiguchi, Masayuki Dohi, Tsuyoshi Matsumura, Hideo Numata, Mari Otsuka, Naoko Yamaguchi, Takashi Shirono, Satoshi Hongo
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Patent number: 8063462Abstract: A semiconductor device includes a semiconductor substrate having a first surface in which a light-receiving portion and electrodes are provided. The semiconductor substrate has a penetrating wiring layer connecting the first surface and the second surface. A light-transmissive protective member is disposed on the semiconductor substrate so as to cover the first surface. A gap is provided between the semiconductor substrate and the light-transmissive protective member. A protective film is formed at a surface of the light-transmissive protective member. The protective film has an opening provided at a region corresponding to the light-receiving portion.Type: GrantFiled: September 18, 2008Date of Patent: November 22, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kazumasa Tanida, Masahiro Sekiguchi, Susumu Harada
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Publication number: 20110241180Abstract: A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface of the semiconductor substrate opposite to a first main surface thereof facing to the supporting substrate to reduce a thickness of the semiconductor substrate to a predetermined thickness.Type: ApplicationFiled: June 20, 2011Publication date: October 6, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masahiro Sekiguchi, Eiji Takano, Tatsuhiko Shirakawa, Kenichiro Hagiwara, Masayuki Dohi, Susumu Harada
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Patent number: 7993974Abstract: A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface of the semiconductor substrate opposite to a first main surface thereof facing to the supporting substrate to reduce a thickness of the semiconductor substrate to a predetermined thickness.Type: GrantFiled: September 24, 2008Date of Patent: August 9, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masahiro Sekiguchi, Eiji Takano, Tatsuhiko Shirakawa, Kenichiro Hagiwara, Masayuki Dohi, Susumu Harada
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Publication number: 20110068476Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate having first and second main surfaces, and a through hole passing through between the first and second main surfaces, a pad on the first main surface, a through electrode in the through hole, and a connection structure including a connection portion to directly connect the pad and the through electrode, and another connection portion to indirectly connect the pad and the through electrode. The method includes forming an isolation region in the first main surface, the isolation region being in a region where the through electrode is to be formed and being in a region other than the region where the through hole is to be formed, forming the pad, and forming the through hole by processing the substrate to expose a part of the pad.Type: ApplicationFiled: September 3, 2010Publication date: March 24, 2011Inventors: Atsuko KAWASAKI, Kenichiro Hagiwara, Ikuko Inoue, Kazutaka Akiyama, Itsuko Sakai, Mie Matsuo, Masahiro Sekiguchi, Yoshiteru Koseki, Hiroki Neko, Koushi Tozuka, Kazuhiko Nakadate, Takuto Inoue
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Patent number: 7888760Abstract: A solid state imaging device includes: an imaging device substrate with an imaging device section formed on a first major surface side thereof; a backside interconnect electrode provided on a second major surface side of the imaging device substrate and electrically connected to the imaging device section, the second major surface being on the opposite side of the first major surface; a circuit substrate provided with a circuit substrate electrode opposed to the second major surface; a connecting portion electrically connecting the backside interconnect electrode to the circuit substrate electrode; and a light shielding layer provided coplanar with the backside interconnect electrode or on the circuit substrate side of the backside interconnect electrode.Type: GrantFiled: October 10, 2008Date of Patent: February 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hitoshi Sugiyama, Atsuko Yamashita, Kazutaka Akiyama, Susumu Harada, Masahiro Sekiguchi, Masayuki Dohi, Kazumasa Tanida, Chiaki Takubo, Hiroshi Yoshikawa, Akihiro Hori
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Patent number: 7888778Abstract: A semiconductor device includes a semiconductor substrate having a through hole. An active layer is formed on a first surface of the semiconductor substrate. An inner wall surface of the through hole, a bottom surface of the through hole closed by the active layer and a second surface of the semiconductor substrate are covered with an insulating layer. A first opening is formed in the insulating layer which is present on the bottom surface of the through hole. A second opening is formed in the insulating layer which is present on the second surface of the semiconductor substrate. A first wiring layer is formed from within the through hole onto the second surface of the semiconductor substrate. A second wiring layer is formed to connect to the second surface through the second opening.Type: GrantFiled: September 9, 2008Date of Patent: February 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kazumasa Tanida, Masahiro Sekiguchi, Ninao Sato, Kenji Takahashi
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Patent number: 7808064Abstract: An imaging element is formed on the first main surface of a semiconductor substrate. An external terminal is formed on the second main surface of the semiconductor substrate. A through-hole electrode is formed in a through hole formed in the semiconductor substrate. A first electrode pad is formed on the through-hole electrode in the first main surface. An interlayer insulating film is formed on the first electrode pad and on the first main surface. A second electrode pad is formed on the interlayer insulating film. A passivation film is formed on the second electrode pad and the interlayer insulating film, and has an opening which exposes a portion of the second electrode pad. A contact plug is formed between the first and second electrode pads in a region which does not overlap the opening when viewed in a direction perpendicular to the surface of the semiconductor substrate.Type: GrantFiled: July 23, 2009Date of Patent: October 5, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Atsuko Kawasaki, Mie Matsuo, Ikuko Inoue, Masayuki Ayabe, Masahiro Sekiguchi, Kazumasa Tanida
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Publication number: 20100025860Abstract: In one aspect of the present invention, a semiconductor device, may include a semiconductor substrate having a first surface and a second surface opposite to the first surface; a through hole in the semiconductor substrate, including an expansion portion which is provided in a vicinity of the first surface so that an opening area of the first opening is greater than an opening area of a lowermost portion of the expansion portion; a first insulating layer on the first surface of the semiconductor substrate; a first wiring layer on the first insulating layer to close the opening of the first insulating layer; a second insulating layer provided on the expansion portion of the through hole; and a second wiring layer on the second insulating layer to extend from inside of the through hole to the second surface of the semiconductor substrate.Type: ApplicationFiled: July 31, 2009Publication date: February 4, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazumasa Tanida, Mie Matsuo, Masahiro Sekiguchi, Chiaki Takubo
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Publication number: 20090284631Abstract: A semiconductor package includes a solid-state imaging element, electrode pad, through-hole electrode, and light-transmitting substrate. The solid-state imaging element is formed on the first main surface of a semiconductor substrate. The electrode pad is formed on the first main surface of the semiconductor substrate. The through-hole electrode is formed to extend through the semiconductor substrate between the first main surface and a second main surface opposite to the electrode pad formed on the first main surface. The light-transmitting substrate is placed on a patterned adhesive to form a hollow on the solid-state imaging element. The thickness of the semiconductor substrate below the hollow when viewed from the light-transmitting substrate is larger than that of the semiconductor substrate below the adhesive.Type: ApplicationFiled: July 29, 2009Publication date: November 19, 2009Inventors: Mie MATSUO, Atsuko Kawasaki, Kenji Takahashi, Masahiro Sekiguchi, Kazumasa Tanida
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Publication number: 20090283847Abstract: An imaging element is formed on the first main surface of a semiconductor substrate. An external terminal is formed on the second main surface of the semiconductor substrate. A through-hole electrode is formed in a through hole formed in the semiconductor substrate. A first electrode pad is formed on the through-hole electrode in the first main surface. An interlayer insulating film is formed on the first electrode pad and on the first main surface. A second electrode pad is formed on the interlayer insulating film. A passivation film is formed on the second electrode pad and the interlayer insulating film, and has an opening which exposes a portion of the second electrode pad. A contact plug is formed between the first and second electrode pads in a region which does not overlap the opening when viewed in a direction perpendicular to the surface of the semiconductor substrate.Type: ApplicationFiled: July 23, 2009Publication date: November 19, 2009Inventors: Atsuko KAWASAKI, Mie Matsuo, Ikuko Inoue, Masayuki Ayabe, Masahiro Sekiguchi, Kazumasa Tanida
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Publication number: 20090194865Abstract: A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface of the semiconductor substrate opposite to a first main surface thereof facing to the supporting substrate to reduce a thickness of the semiconductor substrate to a predetermined thickness.Type: ApplicationFiled: September 24, 2008Publication date: August 6, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masahiro Sekiguchi, Eiji Takano, Tatsuhiko Shirakawa, Kenichiro Hagiwara, Masayuki Dohi, Susumu Harada