Abstract: In a semiconductor memory circuit, a write voltage generation circuit receives an output voltage of a voltage boosting circuit to generate a write voltage to a memory cell. When the write voltage is low, a number-of-bits adjustment circuit increases the number of write bits of memory cells before write operation is performed. On the other hand, when the write voltage to a memory cell is high, the number-of-bits adjustment circuit decreases the number of write bits of memory cells before write operation is performed. The area and write time of the voltage boosting circuit can be reduced while the current supply capability of the voltage boosting circuit is efficiently used.

Abstract: A semiconductor memory device comprises an address terminal through which an address for reading out stored data in a memory array is input, a clock input terminal through which an input clock is input, a data output terminal through which data read out from the memory array in accordance with the address is output, and a clock output terminal through which an output clock synchronous with the input clock is output. The clock output terminal invariably outputs one of a first voltage and a second voltage. Only when valid data is output from the data output terminal, the clock output terminal causes an output voltage to go from the first voltage to the second voltage or from one voltage to the other voltage.

Abstract: In a serial memory device which performs reception and transmission of command, address, and data via serial communication with a host controller, a base address holding circuit holds a base address which serves as a base for effective address calculation. An address operation circuit calculates an effective address based on the base address and an address input from the host controller.

Abstract: A semiconductor memory device includes: a power supply circuit for outputting a power supply voltage used for reading out data; and a power supply circuit status determination circuit for determining whether an operation status of the power supply circuit is such that data can be read out normally. The output of readout data is suppressed while it is determined by the power supply circuit status determination circuit that the operation status is such that data cannot be read out normally.

Abstract: A semiconductor memory device comprises an address terminal through which an address for reading out stored data in a memory array is input, a clock input terminal through which an input clock is input, a data output terminal through which data read out from the memory array in accordance with the address is output, and a clock output terminal through which an output clock synchronous with the input clock is output. The clock output terminal invariably outputs one of a first voltage and a second voltage. Only when valid data is output from the data output terminal, the clock output terminal causes an output voltage to go from the first voltage to the second voltage or from one voltage to the other voltage.

Abstract: In a system of using a plurality of memories with a plurality of CPUs, a plurality of memory arrays are placed on the same memory chip with each memory array being individually provided with a data-related circuit, an address-related circuit and a control-related circuit. These memory arrays however share a data terminal, an address terminal and a control terminal for chip external connection. A data, address and control signals are distributed to the memory arrays via three MUX of signal selection circuits controlled with an array selection signal (clock). A signal is supplied to one memory array at rising timing of the clock while a signal is supplied to another memory array at falling timing of the clock. Thus, in memory integration of placing a plurality of memory arrays on one chip, independent operation for each memory array is attained, and no bus arbitration between CPUs is necessary.

Abstract: A semiconductor memory device includes: a power supply circuit for outputting a power supply voltage used for reading out data; and a power supply circuit status determination circuit for determining whether an operation status of the power supply circuit is such that data can be read out normally. The output of readout data is suppressed while it is determined by the power supply circuit status determination circuit that the operation status is such that data cannot be read out normally.

Abstract: In a system of using a plurality of memories with a plurality of CPUs, a plurality of memory arrays are placed on the same memory chip with each memory array being individually provided with a data-related circuit, an address-related circuit and a control-related circuit. These memory arrays however share a data terminal, an address terminal and a control terminal for chip external connection. A data, address and control signals are distributed to the memory arrays via three MUX of signal selection circuits controlled with an array selection signal (clock). A signal is supplied to one memory array at rising timing of the clock while a signal is supplied to another memory array at falling timing of the clock. Thus, in memory integration of placing a plurality of memory arrays on one chip, independent operation for each memory array is attained, and no bus arbitration between CPUs is necessary.

Abstract: A semiconductor apparatus includes serially-connected bodies composed of a switch element and a resistance element respectively interposed between terminals adjacent to one another, conduction-test terminals connected to one and another ends of a series of the serially-connected bodies, and a switch control terminal for collectively controlling all the plural switch elements. Also included are switch elements interposed alternately on the first semiconductor chip side and the second semiconductor chip side between wires adjacent to one another, conduction-test terminals connected to one and another ends of a series of the serially-connected switch elements, and a switch control terminal for collectively controlling all the plural switch elements.

Abstract: A semiconductor apparatus comprises serially-connected bodies comprised of a switch element and a resistance element respectively interposed between terminals adjacent to one another, conduction-test terminals connected to one and another ends of a series of the serially-connected bodies, and a switch control terminal for collectively controlling all the plural switch elements. Also comprised are switch elements interposed alternately on the first semiconductor chip side and the second semiconductor chip side between wires adjacent to one another, conduction-test terminals connected to one and another ends of a series of the serially-connected switch elements, and a switch control terminal for collectively controlling all the plural switch elements.