Patents by Inventor Masahisa Miyake

Masahisa Miyake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Magnetic disk apparatus and method
    Patent number: 11899968
    Abstract: According to one embodiment, a magnetic disk apparatus is provided with a magnetic disk, a buffer memory, and a control circuit. The magnetic disk has plural bands, each of which is a storage area in which data is written by the method of SMR. The control circuit receives a read request from outside. If the data requested to be read is first data of an update target stored in a first band among plural bands, the control circuit reads the first data from the first band, stores the first data in a buffer memory, and updates the first data in the buffer memory. Then, the control circuit transmits the first data in the buffer memory to the outside and writes the first data in the buffer memory to one of the plural bands.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: February 13, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Masahisa Miyake, Kazuya Takada
  • MAGNETIC DISK APPARATUS AND METHOD
    Publication number: 20230088609
    Abstract: According to one embodiment, a magnetic disk apparatus is provided with a magnetic disk, a buffer memory, and a control circuit. The magnetic disk has plural bands, each of which is a storage area in which data is written by the method of SMR. The control circuit receives a read request from outside. If the data requested to be read is first data of an update target stored in a first band among plural bands, the control circuit reads the first data from the first band, stores the first data in a buffer memory, and updates the first data in the buffer memory. Then, the control circuit transmits the first data in the buffer memory to the outside and writes the first data in the buffer memory to one of the plural bands.
    Type: Application
    Filed: March 8, 2022
    Publication date: March 23, 2023
    Inventors: Masahisa MIYAKE, Kazuya TAKADA
  • Logic circuit design method, logic circuit design program, and logic circuit design system
    Patent number: 8898601
    Abstract: According to one embodiment, a logic circuit design method of an embodiment includes generating logical data corresponding to register transfer level description, based on design data containing the register transfer level description, and generating constraint conditions designating circuit data which satisfies a predetermined condition among plural gate level circuit data logically equivalent to the logical data, based on the design data, and generating gate level circuit data based on the logical data under the constraint conditions.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: November 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahisa Miyake, Kenji Yoshida, Kazumasa Nomura
  • LOGIC CIRCUIT DESIGN METHOD, LOGIC CIRCUIT DESIGN PROGRAM, AND LOGIC CIRCUIT DESIGN SYSTEM
    Publication number: 20140047400
    Abstract: According to one embodiment, a logic circuit design method of an embodiment includes generating logical data corresponding to register transfer level description, based on design data containing the register transfer level description, and generating constraint conditions designating circuit data which satisfies a predetermined condition among plural gate level circuit data logically equivalent to the logical data, based on the design data, and generating gate level circuit data based on the logical data under the constraint conditions.
    Type: Application
    Filed: July 22, 2013
    Publication date: February 13, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masahisa Miyake, Kenji Yoshida, Kazumasa Nomura