Patents by Inventor Masahito Takahashi

Masahito Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10991510
    Abstract: A dielectric membrane may be exposed to an acid solution such as hydrochloric acid, nitric acid, or sulfuric acid during a wet process after membrane formation. The inventors have newly found that when a dielectric membrane includes Ca having a lower ionization tendency than Ba and Zr having a lower ionization tendency than Ti in a main component of a metal oxide expressed by a general formula (Ba, Ca)(Ti, Zr)O3 and satisfies at least one of degree of orientation of (100) plane>degree of orientation of (110) plane and degree of orientation of (111) plane>degree of orientation of (110) plane in a membrane thickness direction, the dielectric membrane is less likely to be damaged during a wet process, and the resistance to a wet process is improved.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: April 27, 2021
    Assignee: TDK CORPORATION
    Inventors: Saori Takahashi, Masahito Furukawa, Masamitsu Haemori, Hiroki Uchiyama, Wakiko Sato, Hitoshi Saita
  • Publication number: 20140191533
    Abstract: Provided is a pillar trim (30) (a vehicle interior trim) with a main body part (32) formed in a hollow, three-dimensional structure by a thermoplastic synthetic resin. The exterior surface of the main body part (32) has a structure whereby an attachment surface (32a) attached to a vehicle structural member and a design surface (32b) inside the vehicle which are both joined together. In addition, the main body part (32) is formed of a bag-like construction that restricts the flow of internal air to the outside, and the main body part (32) distributes and absorbs impact forces from passenger during vehicle impact by using the internal pressure thereof.
    Type: Application
    Filed: June 20, 2011
    Publication date: July 10, 2014
    Applicant: HOWA TEXTILE INDUSTRY CO., LTD
    Inventor: Masahito Takahashi
  • Publication number: 20060214254
    Abstract: To suppress occurrence of defects in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.
    Type: Application
    Filed: May 31, 2006
    Publication date: September 28, 2006
    Inventors: Norio Ishitsuka, Tomio Iwasaki, Hiroyuki Ohta, Hideo Miura, Masahito Takahashi, Norio Suzuki, Shuji Ikeda, Hideki Tanaka, Hiroyuki Mima
  • Patent number: 7084477
    Abstract: To suppress defects occurred in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: August 1, 2006
    Assignees: Hitachi, Ltd., Trecenti Technologies, Inc.
    Inventors: Norio Ishitsuka, Tomio Iwasaki, Hiroyuki Ohta, Hideo Miura, Masahito Takahashi, Norio Suzuki, Shuji Ikeda, Hideki Tanaka, Hiroyuki Mima
  • Patent number: 6787411
    Abstract: Disclosed are a gain cell structure capable of making a memory cell compact in size and a method of manufacturing the same at low cost. A memory cell is constituted of a reading MIS transistor and a writing MIS transistor. The reading MIS transistor has a pair of n+ type semiconductor regions (source region and drain region) formed on a main surface of a semiconductor substrate and a first gate electrode formed on a path of the n+ type semiconductor regions 13 via a first gate insulating film. The writing MIS transistor is arranged on the reading MIS transistor and has a layered structure made by laminating a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) in this order. The writing MIS transistor has a vertical structure in which a second gate electrode is arranged on both sidewalls of the layered structure via a second gate insulating film.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: September 7, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Teruaki Kisu, Kazuo Nakazato, Masahito Takahashi
  • Patent number: 6714447
    Abstract: It is possible to suppress or prevent so-called write disturbance phenomenon from occurring in write-disabled non-selected memory cells in a semiconductor device, in any selected one of which data can be written electrically by means of the so-called tunneling phenomenon. In a flash memory that can disable writing of data by suppressing injection of electrons in the accumulation layer of each non-selected memory cell in which data is to be written with a writing disable voltage applied to the drain thereof before a write voltage is applied to the control gate electrode of each selected memory cell, the relationship among a writing disable voltage Vwd, a read voltage Vr applied to the drain of a selected memory cell from which data is to be read, and a punch-through withstand voltage BVds between the source and the drain of each selected memory cell is set to satisfy Vr<BVds<Vwd.
    Type: Grant
    Filed: March 1, 2002
    Date of Patent: March 30, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Akihiko Satoh, Masahito Takahashi
  • Publication number: 20040058499
    Abstract: To suppress defects occurred in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.
    Type: Application
    Filed: June 23, 2003
    Publication date: March 25, 2004
    Inventors: Norio Ishitsuka, Tomio Iwasaki, Hiroyuki Ohta, Hideo Miura, Masahito Takahashi, Norio Suzuki, Shuji Ikeda, Hideki Tanaka, Hiroyuki Mima
  • Patent number: 6646303
    Abstract: The present invention aims to provide high integration of a nonvolatile semiconductor memory device having lots of flash memory cells without causing a reduction in its operating speed. A width taken along a gate-width direction, of a lower conductor film for a floating gate electrode is made thinner than a minimum processing size F, and a width taken along the gate-width direction, of an upper conductor film for the floating gate electrode, which is provided with an insulating film disposed on source and drain regions interposed therebetween, is made thicker than the minimum processing size F, whereby a reduction in the ratio of coupling between a control gate electrode and a floating gate electrode due to the scaling down of a unit cell area is restrained.
    Type: Grant
    Filed: October 10, 2001
    Date of Patent: November 11, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Akihiko Satoh, Masahito Takahashi, Takayuki Yoshitake
  • Publication number: 20030129001
    Abstract: Disclosed are a gain cell structure capable of making a memory cell compact in size and a method of manufacturing the same at low cost. A memory cell is constituted of a reading MIS transistor and a writing MIS transistor. The reading MIS transistor has a pair of n+ type semiconductor regions (source region and drain region) formed on a main surface of a semiconductor substrate and a first gate electrode formed on a path of the n+ type semiconductor regions 13 via a first gate insulating film. The writing MIS transistor is arranged on the reading MIS transistor and has a layered structure made by laminating a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) in this order. The writing MIS transistor has a vertical structure in which a second gate electrode is arranged on both sidewalls of the layered structure via a second gate insulating film.
    Type: Application
    Filed: December 30, 2002
    Publication date: July 10, 2003
    Inventors: Teruaki Kisu, Teruo Kisu, Haruko Kisu, Kazuo Nakazato, Masahito Takahashi
  • Patent number: 6501116
    Abstract: Disclosed are a gain cell structure capable of making a memory cell compact in size and a method of manufacturing the same at low cost. A memory cell is constituted of a reading MIS transistor and a writing MIS transistor. The reading MIS transistor has a pair of n+ type semiconductor regions (source region and drain region) formed on a main surface of a semiconductor substrate and a first gate electrode formed on a path of the n+ type semiconductor regions 13 via a first gate insulating film. The writing MIS transistor is arranged on the reading MIS transistor and has a layered structure made by laminating a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) in this order. The writing MIS transistor has a vertical structure in which a second gate electrode is arranged on both sidewalls of the layered structure via a second gate insulating film.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: December 31, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Teruaki Kisu, Kazuo Nakazato, Masahito Takahashi
  • Publication number: 20020158273
    Abstract: The present invention aims to provide high integration of a nonvolatile semiconductor memory device having lots of flash memory cells without causing a reduction in its operating speed. A width taken along a gate-width direction, of a lower conductor film for a floating gate electrode is made thinner than a minimum processing size F, and a width taken along the gate-width direction, of an upper conductor film for the floating gate electrode, which is provided with an insulating film disposed on source and drain regions interposed therebetween, is made thicker than the minimum processing size F, whereby a reduction in the ratio of coupling between a control gate electrode and a floating gate electrode due to the scaling down of a unit cell area is restrained.
    Type: Application
    Filed: October 10, 2001
    Publication date: October 31, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Akihiko Satoh, Masahito Takahashi, Takayuki Yoshitake
  • Publication number: 20020141240
    Abstract: To suppress or prevent the so-called write disturbance phenomenon from occurring in write-disabled non-selected memories in a semiconductor device provided with a plurality of memory cells, in any selected one of which data can be written electrically by means of the so-called tunneling phenomenon. In a flash memory that can disable writing of data by suppressing injection of electrons in the accumulation layer of each non-selected memory cell in which data is to be written with a writing disable voltage applied to the drain thereof before a write voltage is applied to the control gate electrode of each selected memory cell, the relationship among a writing disable voltage Vwd, a read voltage Vr applied to the drain of a selected memory cell from which data is to be read, and a punch-through withstand voltage BVds between the source and the drain of each selected memory cell is set so as to satisfy Vr<BVds<Vwd.
    Type: Application
    Filed: March 1, 2002
    Publication date: October 3, 2002
    Inventors: Akihiko Satoh, Masahito Takahashi
  • Publication number: 20020098639
    Abstract: Disclosed are a gain cell structure capable of making a memory cell compact in size and a method of manufacturing the same at low cost. A memory cell is constituted of a reading MIS transistor and a writing MIS transistor. The reading MIS transistor has a pair of n+ type semiconductor regions (source region and drain region) formed on a main surface of a semiconductor substrate and a first gate electrode formed on a path of the n+ type semiconductor regions 13 via a first gate insulating film. The writing MIS transistor is arranged on the reading MIS transistor and has a layered structure made by laminating a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) in this order. The writing MIS transistor has a vertical structure in which a second gate electrode is arranged on both sidewalls of the layered structure via a second gate insulating film.
    Type: Application
    Filed: December 27, 2001
    Publication date: July 25, 2002
    Inventors: Teruaki Kisu, Kazuo Nakazato, Masahito Takahashi, Teruo Kisu, Haruko Kisu
  • Patent number: 6423584
    Abstract: A gate electrode of a field-effect transistor used as a peripheral circuit is constituted by the same gate electrode structure as a double-level gate electrode structure of nonvolatile memory cells, and a contact hole for connecting those conductive films constituting the gate electrode is provided at a location which two-dimensionally overlaps an active area within a plane of the gate electrode. A hole for connecting between the two layers of the gate electrode of a first field-effect transistor used as perpheral circuit is provided at a location which two-dimensionally overlaps the active area within the plane of the gate electrode, and a hole for connecting between the two layers of the gate electrode of a second field-effect transistor used as a peripheral circuit is provided at a location which two-dimensionally overlaps an isolation area within the plane of the gate electrode.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: July 23, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Masahito Takahashi, Shiro Akamatsu, Akihiko Satoh, Fukuo Owada, Masataka Kato
  • Patent number: 6420754
    Abstract: A gate electrode of a field-effect transistor used as a peripheral circuit is constituted by the same gate electrode structure as a double-level gate electrode structure of nonvolatile memory cells. A hole for connecting the two layers of the gate electrode of a first field-effect transistor used as peripheral circuit is provided at a location which two-dimensionally overlaps the active area within the plane of the gate electrode, and a hole for connecting the two layers of the gate electrode of a second field-effect transistor used as a peripheral circuit is provided at a location which two-dimensionally overlaps an isolation area within the plane of the gate electrode. The gate length of the first field-effect transistor is longer than the gate length of the second field-effect transistor, and the gate width of the first field-effect transistor is wider than the gate width of the second field-effect transistor.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: July 16, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Masahito Takahashi, Shiro Akamatsu, Akihiko Satoh, Fukuo Owada, Masataka Kato
  • Publication number: 20010024859
    Abstract: A gate electrode of a field-effect transistor used as a peripheral circuit is constituted by the same gate electrode structure as a double-level gate electrode structure of nonvolatile memory cells, and a contact hole for connecting those conductive films constituting the gate electrode is provided at a location which two-dimensionally overlaps an active area within a plane of the gate electrode.
    Type: Application
    Filed: March 20, 2001
    Publication date: September 27, 2001
    Inventors: Masahito Takahashi, Shiro Akamatsu, Akihiko Satoh, Fukuo Owada, Masataka Kato
  • Publication number: 20010020718
    Abstract: A gate electrode of a field-effect transistor used as a peripheral circuit is constituted by the same gate electrode structure as a double-level gate electrode structure of nonvolatile memory cells, and a contact hole for connecting those conductive films constituting the gate electrode is provided at a location which two-dimensionally overlaps an active area within a plane of the gate electrode.
    Type: Application
    Filed: February 26, 2001
    Publication date: September 13, 2001
    Inventors: Masahito Takahashi, Shiro Akamatsu, Akihiko Satoh, Fukuo Owada, Masataka Kato
  • Patent number: 5898621
    Abstract: A batch erasable single chip nonvolatile memory device and a method therefor of using the same provided with memory cells which are adapted to execute an erase operation by ejecting an electric charge, accumulated at floating gates by a program operation (including a pre-write operation) carries out, in sequence a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvo
    Type: Grant
    Filed: July 31, 1997
    Date of Patent: April 27, 1999
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Masahito Takahashi, Michiko Odagiri, Takeshi Furuno, Kazunori Furusawa, Masashi Wada
  • Patent number: 5677868
    Abstract: A batch erasable nonvolatile memory device and an apparatus using the same provided with memory cells which are adapted to execute an erase operation by ejecting an electric charge, accumulated at floating gates by a program operation (including a pre-write operation), carries out, in sequence, a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvolatile memory cell
    Type: Grant
    Filed: October 31, 1996
    Date of Patent: October 14, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Masahito Takahashi, Michiko Odagiri, Takeshi Furuno, Kazunori Furusawa, Masashi Wada
  • Patent number: 5598368
    Abstract: A batch erasable nonvolatile memory device and an apparatus using the same provided with memory cells which are adapted to execute an erase operation by a ejecting an electric charge accumulated at floating gates by program operation (including a pre-write operation), carries out, in sequence, a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvolatile memory cells
    Type: Grant
    Filed: May 19, 1995
    Date of Patent: January 28, 1997
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Masahito Takahashi, Michiko Odagiri, Takeshi Furuno, Kazunori Furusawa, Masashi Wada