Patents by Inventor Masakazu Hirose

Masakazu Hirose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6975147
    Abstract: A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: December 13, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Hideto Hidaka, Masakazu Hirose
  • Patent number: 6965148
    Abstract: In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: November 15, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Masakazu Hirose, Fukashi Morishita
  • Patent number: 6914300
    Abstract: In a potential interconnection layer, when viewed from a plane, a plurality of power supply potential regions and ground potential regions are alternately provided, with an interlayer insulation layer lying therebetween. A contact plug penetrating a second insulation layer is provided to electrically connect a source/drain (S/D) region on one side of a selected field effect transistor with a selected power supply potential region. Similarly, a contact plug penetrating the second insulation layer is provided to electrically connect a source/drain (S/D) region on the other side of another selected field effect transistor with a selected ground potential region. By employing this structure, a semiconductor device having a plurality of semiconductor circuits in which a power supply potential and a ground potential can be stabilized regardless of the cross-sectional structure of the semiconductor device is provided.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: July 5, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Masakazu Hirose, Fukashi Morishita
  • Publication number: 20050075235
    Abstract: There are provided steps of polarizing a ceramic composition including a perovskite compound containing Pb, Zr, Ti and Mn as main components and a heat treatment step for keeping the polarized ceramic composition within a temperature range lower than Tc (Tc denoting the Curie temperature of the ceramic composition) for 1 to 100 minutes.
    Type: Application
    Filed: September 24, 2004
    Publication date: April 7, 2005
    Inventors: Tomohisa Azuma, Masakazu Hirose
  • Publication number: 20040257112
    Abstract: A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused.
    Type: Application
    Filed: July 15, 2004
    Publication date: December 23, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Hideto Hidaka, Masakazu Hirose
  • Publication number: 20040201062
    Abstract: In a potential interconnection layer, when viewed from a plane, a plurality of power supply potential regions and ground potential regions are alternately provided, with an interlayer insulation layer lying therebetween. A contact plug penetrating a second insulation layer is provided to electrically connect a source/drain (S/D) region on one side of a selected field effect transistor with a selected power supply potential region. Similarly, a contact plug penetrating the second insulation layer is provided to electrically connect a source/drain (S/D) region on the other side of another selected field effect transistor with a selected ground potential region. By employing this structure, a semiconductor device having a plurality of semiconductor circuits in which a power supply potential and a ground potential can be stabilized regardless of the cross-sectional structure of the semiconductor device is provided.
    Type: Application
    Filed: September 3, 2003
    Publication date: October 14, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Masakazu Hirose, Fukashi Morishita
  • Patent number: 6777986
    Abstract: A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused.
    Type: Grant
    Filed: August 14, 2002
    Date of Patent: August 17, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Hideto Hidaka, Masakazu Hirose
  • Patent number: 6685850
    Abstract: The invention provides a piezoelectric ceramic material comprising a Bi3TiNbO9 crystal and/or an MBi2Nb2O9 crystal which are each a bismuth layer compound, where M represents at least one element selected from Sr, Ba and Ca. The ceramic material contains Bi, Ti, M and Nb as main component elements. The molar ratio as oxides of the main component elements is given by (Bi3−xMx)z (Nb1+yTi1−y)O9 provided that 0<x, y≦0.8 and 0.95≦z≦1.05. When the molar ratio of Ba/(M+Bi) is given by xB/3 and the molar ratio of Ca/(M+Bi) is given by xC/3, it is required that 0≦xB≦0.5 and 0≦xC<0.4. This piezoelectric ceramic material, free from any lead whatsoever, has a sufficiently high Curie point, and exhibits ever more improved piezoelectric properties.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: February 3, 2004
    Assignee: TDK Corporation
    Inventors: Masaru Nanao, Masakazu Hirose, Takeo Tsukada
  • Patent number: 6551522
    Abstract: Piezoelectric ceramics include a bismuth layer compound containing MII, Bi, Ti, Ln and O, wherein MII represents at least one element selected from the group consisting of Sr, Ba and Ca, and Ln represents at least one element selected from the group consisting of lanthanoids. The piezoelectric ceramics include MIIBi4Ti4O15 typed crystals, and a mole ratio of Ln/(Ln+MII) is 0<Ln/(Ln+MII)<0.5. In the case where MII is Sr, a mole ratio of 4Bi/Ti is 4.000<4Bi/Ti≦4.030. Preferably, piezoelectric ceramics further include Y oxide.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: April 22, 2003
    Assignee: TDK Corporation
    Inventors: Masakazu Hirose, Takeo Tsukada, Hitoshi Oka, Junji Terauchi
  • Publication number: 20030057488
    Abstract: In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.
    Type: Application
    Filed: August 21, 2002
    Publication date: March 27, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masakazu Hirose, Fukashi Morishita
  • Publication number: 20020196057
    Abstract: A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused.
    Type: Application
    Filed: August 14, 2002
    Publication date: December 26, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideto Hidaka, Masakazu Hirose
  • Patent number: 6461532
    Abstract: A piezoelectric ceramic material comprising a bismuth layer compound containing MII, Bi, Ti and O wherein MII is selected from Sr, Ba and Ca, and containing MIIBi4Ti4O15 type crystals, wherein MII, is represented by SrxBayCaz wherein x+y+z=1, utilizes thickness shear vibration when 0≦x≦ 1, 0≦y≦0.9, and 0≦z≦1, and thickness extensional vibration when 0≦x<0.9, 0≦y≦0.9, and 0≦z<1. Also provided is a piezoelectric ceramic material comprising a bismuth layer compound containing Ca, Bi, Ti, Ln and 0 wherein Ln is a lanthanoid, and containing CaBi4Ti4O15 type crystals, wherein the atomic ratio Ln/(Ln+Ca) is in the range: 0<Ln/(Ln+Ca)<0.5. These piezoelectric ceramic materials are free of lead, and have a high Curie point and improved piezoelectric characteristics.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: October 8, 2002
    Assignee: TDK Corporation
    Inventors: Hitoshi Oka, Masakazu Hirose, Yasuo Watanabe, Junji Terauchi
  • Patent number: 6452861
    Abstract: The SDRAM is provided with a decoder for generating four inversion instruction signals corresponding to four data signals according to a column address signal not used for a column select and a word configuration activating signal, and a data inverting circuit for outputting each data signal inverted or uninverted according to four inversion instruction signals. Thus, four data signals of the “H” level can be input so as to write in a desired test pattern with ease.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: September 17, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Masakazu Hirose
  • Patent number: 6445222
    Abstract: A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused.
    Type: Grant
    Filed: November 9, 2000
    Date of Patent: September 3, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideto Hidaka, Masakazu Hirose
  • Patent number: 6404102
    Abstract: A piezoelectric substrate is constituted by a piezoelectric material of an effective Poisson's ratio being less than 1/3. The substrate has a pair of opposite faces and the opposite faces are provide with a pair of vibrating electrodes in correspondence. The opposite faces of the piezoelectric substrate are rectangular respectively. The sum of the lengths Lc of the one faces in the opposite faces 1a, 1b and the length Wc of the other side of the same is limited within range 2.22 mm≦≦2.24 mm or 2.34 mm≦≦2.48 mm, said one faces being vertical each other. The areas Sc of the opposite faces are 1.22 mm2≦Sc≦1.26 mm2 or 1.35 mm2≦Sc≦1.538 mm2. Accordingly, though using the piezoelectric material of the effective Poisson's ratio being less than 1/3, vibration in the thickness extensional fundamental waves can be steadily utilized.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: June 11, 2002
    Assignee: TDK Corporation
    Inventors: Toshiyuki Suzuki, Nobuyuki Miki, Masakazu Hirose, Masayoshi Inoue
  • Patent number: 6398978
    Abstract: A piezoelectric ceramic is a bismuth-layer compound having SrBi4Ti4O15-type crystal. The axial ratio c/a of crystal lattice is in the range of 7.46 to 7.67.
    Type: Grant
    Filed: June 13, 2000
    Date of Patent: June 4, 2002
    Assignee: TDK Corporation
    Inventors: Masakazu Hirose, Hitoshi Oka, Takeo Tsukada
  • Publication number: 20020035027
    Abstract: The invention provides a piezoelectric ceramic material comprising a Bi3TiNbO9 crystal and/or an MBi2Nb2O9 crystal which are each a bismuth layer compound, where M represents at least one element selected from Sr, Ba and Ca. The ceramic material contains Bi, Ti, M and Nb as main component elements. The molar ratio as oxides of the main component elements is given by (Bi3−xMx)z (Nb1+yTi1−y)O9 provided that 0<x, y≦0.8 and 0.95≦z≦1.05. When the molar ratio of Ba/(M+Bi) is given by xB/3 and the molar ratio of Ca/(M+Bi) is given by xc/3, it is required that 0≦xB≦0.5 and 0≦xC<0.4. This piezoelectric ceramic material, free from any lead whatsoever, has a sufficiently high Curie point, and exhibits ever more improved piezoelectric properties.
    Type: Application
    Filed: July 27, 2001
    Publication date: March 21, 2002
    Applicant: TDK CORPORATION
    Inventors: Masaru Nanao, Masakazu Hirose, Takeo Tsukada
  • Publication number: 20020003730
    Abstract: The semiconductor memory device has a word configuration determination signal generating circuit including a plurality of generating circuits, each of which is formed of two clocked inverters and two inverters. In a normal operation mode, a test mode signal TX4 is inactivated and a word configuration determination signal [×16E] of an H level is output. In a test mode, the test mode signal TX4 is activated and a word configuration determination signal [×4E] of an H level is output. Thus, in the test mode, the word configuration is switched to the one that is smaller than in the normal operation mode. This allows simultaneous testing of a larger number of semiconductor memory devices.
    Type: Application
    Filed: December 4, 2000
    Publication date: January 10, 2002
    Inventors: Shigekazu Aoki, Seiji Sawada, Mikio Asakura, Takeshi Hamamoto, Masakazu Hirose
  • Patent number: 6335887
    Abstract: The semiconductor memory device has a word configuration determination signal generating circuit including a plurality of generating circuits, each of which is formed of two clocked inverters and two inverters. In a normal operation mode, a test mode signal TX4 is inactivated and a word configuration determination signal [x16E] of an H level is output. In a test mode, the test mode signal TX4 is activated and a word configuration determination signal [x4E] of an H level is output. Thus, in the test mode, the word configuration is switched to the one that is smaller than in the normal operation mode. This allows simultaneous testing of a larger number of semiconductor memory devices.
    Type: Grant
    Filed: December 4, 2000
    Date of Patent: January 1, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigekazu Aoki, Seiji Sawada, Mikio Asakura, Takeshi Hamamoto, Masakazu Hirose
  • Patent number: RE38213
    Abstract: A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: August 12, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideto Hidaka, Masakazu Hirose